SRAM Clock Frequency for STM32N657X0H3Q (Nucleo-N657X0-Q)

[A_sharma]

Hi ST team,

I'm working with the Nucleo-N657X0-Q board (STM32N657X0H3Q MCU) and running the nx_iperf example from NetX Duo. I’d like to understand what the SRAM clock frequency is during this example's execution. In the release notes, it’s mentioned that the core clock is set to 600 MHz, although the maximum supported core clock is 800 MHz. I’m trying to determine:

• What is the default clock source and frequency for the SRAM in this MCU?
• Is the SRAM clock configurable separately from the system clock?

Any guidance or documentation references would be greatly appreciated.

 

Thankyou, 

A. Sharma

[STackPointer64]

Hello @A_sharma, and welcome to ST Community!

The SRAM is typically connected to the AXI bus or AHB bus so by default, the SRAM is clocked by the HCLK, which is usually set equal to the SYSCLK unless divided.

Best regards,

 

[RomainR.]

Hi @A_sharma 

The STM32N6 has a CPUSW SYSA_CLK frequency of:

• Maximum 800MHz in VOS High mode at VDDCORE=0.89V

• Maximum 600MHz in VOS Low mode at VDDCORE=0.81V

Refer to RM0486, Figure 130. Neural-ART 14 integration and Figure 1. Interconnect top view - STM32N6x7 devices. The AXI NOC bus frequency is 400MHz.
The internal SRAMs are clocked by the following sources:

• AXISRAM1/2 clocks: derived from sysb_ck.

• AXISRAM3/4/5/6 clocks: derived from sysd_ck.

In the NeXduo Nx_Iperf example, the frequencies are configured as:
SYSCLK AXI (sysb_ck) (Hz) = 400MHz
SSCLK AXISRAM3/4/5/6 (sysd_ck) (Hz) = 400MHz
Refer to SystemClock_Config() in main.c file.

Best regards,

Romain,