STM32H7S78-DK PSRAM bringup (psram parameters)

[yakabmarci]

I am trying to run some basic tests on the STM32H7S78-DK discovery board.

I am having some trouble properly initializing the PSRAM (is this info available somewhere, what are the right settings?)

PSRAM is clocked at 200MHz, i copied settings from the available examples/bsp

I am having random errors, it looks like that sometimes the write is not executed

Most of the time like 99.99% of the case, everything works fine, but sometimes i read old data from the PSRAM, this mostly happens with 16 or 8 bit r/w but rarely also with 32 bit r/w

I have a test that writes the whole ram with some pattern then verifies it.

This happens in all combination of cache settings, but cache settings have a significant impact on the frequency of these errors (not clear why).

i'm logging the result, it looks something like this:

T32 for pattern 0fc52bc8 0 diff
T16 for pattern 00007118 0 diff
T8 for pattern 000000bb 0 diff
T32 for pattern 4fa30e48 0 diff
T16 for pattern 00005498 0 diff
T8 for pattern 0000003b 0 diff
T32 for pattern b4cf54f8 0 diff
T16 for pattern 00000e28

diff @ 0x91209040 : 0x54f8
diff @ 0x91209042 : 0xb4cf
diff @ 0x91209044 : 0x54f8
diff @ 0x91209046 : 0xb4cf
diff @ 0x91209048 : 0x54f8
diff @ 0x9120904a : 0xb4cf
diff @ 0x9120904c : 0x54f8
diff @ 0x9120904e : 0xb4cf
8 diff

For the last T16 test, i.e. overwrite the whole PSRAM content with 0x0e28, using 16bit access, there are 8 differences at 8 consecutive memory locations, where the write silently failed and the old data from the previous test is still present.

Any ideas or suggestions on how to debug this? I can not physically check/measure the lines between mcu and psram as they are not accessible, neither i have the equipment for it.

 

 

 

[CYANG.1]

Hi,

I think you may reduce the work frequency to check whether such problem is still happened. another method is to change the clock phase to sample read data from PSRAM.

 

B.R.

[yakabmarci]

i would not like to reduce clock frequency as it comes with performance hit, both the mcu and the psram is rated up to 200Mhz. I could play with various settings, but i will never know for sure, as i can't make physical measurements on the xspi lines.

 

Given that this is a fixed HW, designed and verified by ST, such parameters should be available that are optimal and are guaranteed to work (golden reference)

[alessandro.breuza]

Struggling on PSRAM random errors, I found on APS256 datasheet default setting at 5 latency cycles (read/write) corresponding to 133MHz max.

 

I have modified EXTMEM_MANAGER config as

to set 7 latency cycles (200MHz max) and now deep-testing...

 

Alessandro