Cannot access memory at address SRAM3: 0x34200000

[stmobject]

Hello

 

I've been trying to recreate the DCMIPP_SnapshotDecimation example with STM32CubeIDE, I have been running into several issues. I have solved most of them, I am encountering a memory error while debugging my code. I was able to flash and debug the original example successfully on the STM32N6570-DK. However, when I try to read a value from the AXISRAM address (0x34200000), it fails: (address does not exist and unable to reconnect to target device).

 

AXISRAM3 which it should be the address 0x3420000 is activated and initialized in the main. 
Initialization of  the signal processor and starting the DCMIPP pipeline was passed without any problem:

if( ISP_Init(&hcamera_isp, &hdcmipp, 0, &appliHelpers, ISP_IQParamCacheInit[0] ) != ISP_OK )
{
 Error_Handler();
}

if( HAL_DCMIPP_CSI_PIPE_Start(&hdcmipp, DCMIPP_PIPE1, DCMIPP_VIRTUAL_CHANNEL0, BUFFER_ADDRESS, DCMIPP_MODE_CONTINUOUS ) != HAL_OK )
{
 Error_Handler();
}

But, trying to access the buffer address throws this error: Cannot access memory at address 0x34200000, which is the value of BUFFER_ADDRESS parameter


Thank you in advance for your response and help. I will appreciate it 

---

Edited to apply source code formatting - please see How to insert source code for future reference.

[Khaled_DHIF]

Hello @stmobject ,

0x34200000 is in an NPU-associated SRAM bank, so the HOST CPU/debugger may not be able to read it unless that region is explicitly configured as shared and accessible. The fact that ISP_Init() and HAL_DCMIPP_CSI_PIPE_Start() succeed does not guarantee that direct CPU access to the buffer is valid. In your recreated project, the most likely issue is a mismatch in memory configuration compared with the original example especially the linker script, MPU setup, and cache/shared-memory settings. The safest test is to place BUFFER_ADDRESS in a known CPU-accessible RAM region first; if that works, then the problem is definitely the AXISRAM/NPU memory configuration rather than DCMIPP itself. 

You can see these memories in this block diagram:

You can find out more about the NPU memory subsystem in this link.

Kind regards, 

DHIF Khaled