STM32 MCUs Embedded software

When I calling NVIC_SystemReset() in the os task, the system will enter into hard fault handler error, so I have to call NVIC_SystemReset() again in the HardFault_Handler() to reset the system, so what is the proper way to call NVIC_SystemReset() in the os task?  

The STRD/LDRD instructions store and load a 64-bit value. Internally, they are broken up into 2x 32-bit accesses.Since the element size is a word and not a double-word, they are not atomic in the same way that a uint32_t is atomic. Questions are:Is this instruction interruptible between the first and second 32-bit accesses?If the instruction does get interrupted, does it restart or resume? If it restarts, it will re-write the first word, for a total of 3x 32-bit accesses. If it resumes, it will only write the last word.The ARM reference manual has this to say on the subject:https://developer.arm.com/documentation/ddi0403/latestTo me, it seems they are restarted based on this text, but the two "might" words here leave ambiguity. But let's not rely on manuals or what people say on the internet. What actually happens in the hardware?

We are using the NUCLEO-H753ZI family of boards with the specific MCU being STM32H753ZIT6. We were following this tutorial: https://community.st.com/t5/stm32-mcus/how-to-create-a-project-for-stm32h7-with-ethernet-and-lwip-stack/ta-p/49308/page/2/show-comments/true The difference between the hardware used in the tutorial and the hardware we use is that instead MII, which is what is used in the tutorial, we are using RMII Even though we were following the tutorial to the dot, our implementation is still not working. We have reverted back from the lasted implementation of STM32CubeIDE to STM32CubeIDE 1.9.0 as mentioned in the tutorial as well. CURRENT DIAGNOSIS:  We have confirmed with a digital oscilloscope that when we are pinging the STM32H753ZIT6, the CRS_DV Pin, which is pin 11, is not going high at all. We have observed, using the oscilloscope, that in our PHY (LAN8742A) on pin 8 that we are able to receive packets and that it is unable to transmit packets using TX pins. T

I am wishing to write two floating point values to flash memory at time.  I understand it is best to write 64 bits at a time, hence my writing two floats at once. This question is about using a union to structure the data. This code won't compile for the STM32L412KB.  Could someone please show me where I am going wrong? error on line 17.  Thanks.struct dual { float v1; float v2; }; struct dual two_readings = {1.23, 4.56}; union gemini { struct dual left; uint64_t right; }; union gemini value; value.right=0; 

Hi everyone,i am using the stm32g0b1cet6 controller. in which I am working with flash memory. I am using the FLASH_WaitForLastOperation function. In that function, one flash SR register's CFGBSY bit is not reset, and due to that all other flash write and erase processes it not working. this issue is coming randomly. before calling FLASH_WaitForLastOperation function I am clearing error flags as shown below __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PROGERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_SIZERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MISERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_FASTERR);__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); can someone please provide some input ASAP.      

I am able to receive UDP unicast packets on the Nucleo-h563ZI using the netconn API, however I cannot receive broadcast UDP packets (global or subnet). I have attached my lwiopts.h for reference along with the relevant discovery service code below. Note that netif->flags has NETIF_FLAG_BROADCAST set in addition to NETIF_FLAG_ETHARP. I was unable to find any broadcast related settings in the IOC file for the ETH peripheral nor related HAL_ETH_xyz calls. I did try enabling broadcast in the MACFilter, but this had no effect.#define NET_TASK_DISCO_PORT (5555) #define NET_TASK_DISCO_REQUEST "SCPI_DISCOVERY" #define NET_TASK_DISCO_RESPONSE "SCPI_DEVICE" #define NET_TASK_DISCO_RESP_LENGTH (64) // // @brief Discovery application // @return none // static void disco(void *pArgument) { char response[NET_TASK_DISCO_RESP_LENGTH]; uint16_t length; void *pBuffer; void *pSend; struct netbuf *prBuffer; struct netbuf *prSend; trNet *prNet = (trNet*)pArgument; // V

Hi all,I am implementing a protocol over I2C that requires the STM32 part to act as peripheral and respond to host data reads. I get two types of read transactions: random access, where the controller sends the peripheral address with the WRITE bit set, then a memory address to begin reading, then another start and the peripheral address with the READ bit set. And sequential reads, where the controller doesn't specify an address, it just starts reading. To handle this I need to maintain a "next read address" internally. Here's a diagram of the sequential read:I am using HAL APIs successfully and driving this from FreeRTOS. I'm testing it with an Aardvark debugger standing in for the controller and an Analog Discovery 2 watching the bus and decoding it. My task turns on listen mode. I get the expected calls to HAL_I2C_AddrCallback(). I can successfully distinguish the two types of transactions, get the memory address with HAL_I2C_Slave_Seq_Receive_IT() with FIRST_FRAME, and se

Hello,I am working on a UVC (USB Video Class) project using a Nucleo-H755ZI-Q board and Azure RTOS USBX.I have successfully tested the ux_device_video (FS) example on the board. Now, I am trying to migrate this example to High Speed (HS) using an external USB3300 ULPI PHY.[Current Status]Hardware: Nucleo-H755ZI-Q + USB3300 (ULPI interface).Software Stack: X-CUBE-AZRTOS-H7 (USBX).Enumeration: The device is correctly recognized as a "Camera" in the Windows Device Manager without any yellow exclamation marks.Issue: When I open the Windows "Camera" app, it fails with the following error code:0xA00F4243 <CameraReservedByAnotherApp>(0xC00D3704)[Modifications Made]Modified the USB configuration to use High Speed with external PHY (ULPI).Updated the USBX descriptors (Device Descriptor, Configuration Descriptor) to support HS, including the Device Qualifier Descriptor.Ensured the ULPI pins are correctly configured in the HAL initialization.[Observations]The FS version works perfectly. The

Hi, i want to use STM32U385RG (NUCLEO-U385RG-Q) to read and write files on SD using SDMMC (1 bit mode) interface, with FileX in standalone mode. I've successfully tested Fx_File_Edit_Standalone (SRAM) example and SD_ReadWrite_DMA (1 bit mode) example. Following my MX_FileX_Process function: VOID MX_FileX_Process(VOID) { UINT status; ULONG bytes_read; CHAR read_buffer[32]; CHAR data[] = "This is FileX working on STM32"; /* Start application */ printf("FileX Edit Standalone Application Start.\n"); /* Open the sram_disk driver. */ status = fx_media_open(&sram_disk, "STM32_SDIO_DISK", fx_stm32_sd_driver, (VOID *)FX_NULL, (VOID *) fx_sd_media_memory, sizeof(fx_sd_media_memory)); /* Check the media open status. */ if (status != FX_SUCCESS) { Error_Handler(); } printf("SD card opened.\n"); /* Create a file called STM32.TXT in the root directory. */ status = fx_file_create(&sram_disk, "STM32.TXT"); /* Check the create status. */ if (status != FX_SUCCESS)

Hello Everyone, This is the code that I have tried many times and tried to debug as well. I have attached a snapshot of the error of the debugging section (disassembly ). I have not been able to understand what of my code leads to this error , and how to solve this? /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2026 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include

Spent a lot of time on this and found that ST's code omits a key SCSI command which windoze and linux either do not issue or if they do they are not bothered by a non-response. Details around here https://www.eevblog.com/forum/microcontrollers/any-way-to-do-a-fat16-usb-msc-drive-in-2mb-flash/msg6206067/#msg6206067

Dear ST Community, I hope you are doing well. I am currently working with the STM32U5 development board and would like to integrate an SD card module using SPI communication. However, while configuring my project in STM32CubeMX / CubeIDE, I was unable to find the FATFS middleware option under the middleware section. My goal is to use FATFS with an SD card operating in SPI mode. Could you please guide me on how to enable or integrate FATFS for SPI-based SD card communication on the STM32U5 series? If manual integration is required, I would appreciate any official documentation, example projects, or recommended procedures.

Dear Team, I am currently working on an STM32F207-based custom board using Ethernet (RMII with LAN8742A PHY) and LwIP in NO_SYS (bare-metal, no RTOS) mode. I am facing an issue where Ethernet and UART are not functioning correctly in parallel. Project Details: MCU: STM32F207 PHY: LAN8742A (RMII mode, PHY address = 1) LwIP Operating Mode: NO_SYS = 1 (No RTOS) DHCP enabled (also tested with static IP) UART2 used for debug output (blocking HAL_UART_Transmit) Issue Description: When Ethernet (LwIP) is enabled and initialized using MX_LWIP_Init(), UART output stops working. Even simple debug prints placed before Ethernet processing in the main loop are not printed. However: If Ethernet/LwIP is disabled, UART works normally. If MX_LWIP_Init() is commented out, UART works. Ethernet link LEDs indicate that PHY is active. This suggests that enabling Ethernet + LwIP in NO_SYS mode is interfering with system execution or blocking during initialization or processing. Observatio

https://controllerstech.com/stm32-ethernet-hardware-cubemx-lwip-ping/?utm_source=chatgpt.comI followed steps of above website data based to configure Ethernet on stm32h753zi but still ping is failing i cant able to find the exact error can anyone help to tell the exact configuration of this board   

Hello,I am trying to find the project used to create the code loaded on my Nucleo-H563ZI when I first received it.I see several references stating it should be in a Demonstration folder, however I don't see that folder in:...\STM32Cube_FW_H5_V1.6.0\Projects\NUCLEO-H563ZIThat folder has the following folders:ApplicationsExamplesExamples_LLExamples_MIXROT_ProvisioningTemplatesTemplates_LL

For context,  I am new to both USB programming and the STM products (and tools), so I apologize in advance for my ignorance. I am working with an old, existing system, which utilized a USB connection to a processor/EEPROM to store information (a dongle).  As some of the parts have gone end-of-life, we are looking to move to new hardware.   The hope is to mimic the software running on the old hardware so that the new part will work with existing systems in the field, as well as new products. Our existing system runs on Linux with a custom driver communicating with the dongle, and from what I can tell has been coded up as a "vendor device" instead of a "class device". Anyhow, the engineering department selected the STM32C071RBT6 as an appropriate part and have provided a prototype which I am using for development along with the following:STM32CubeIDE   v2.0.0STM32CubeMX    v6.16.1STM32C0 series  v1.4.0 To get started w

I have a STM32H732 processor connected to a ethernet switch with port based VLAN support.I use the processor to connect to two different interfaces which are separated in the switch.I wanted to be able to access the same two TCP ports in the processor from both interfaces.So I configured ETH_L3_FILTER_0 and ETH_L3_FILTER_1 with the two different IP-addresses used on the two interfacesAnd the ETH_L4_FILTER_0 and ETH_L4_FILTER_1 with the two different ports.But that did not work as I hoped.It looks like the L3_FILTER_0 and L4_FILTER_0 are used as one filter. and FILTER_1 as another.And maybe that is as intented but it is not super clear in the documentation.I may have to add that I have found and read...Is this correct or is there perhaps a way to use the L3 and L4 as separate filters so that I can get four different filters allowing two IPs and two Ports in any combination of ports and IP?Best regards 

Dear. AllI'm asking how to use STemWin on stm32h743 mcu.How to add STemWin on STM32CubeIDE? (Current Use Version. 1.13.0)?How can I run a project with the development board I bought? (STM32H743I-EVAL)?In particular, I want to run the STemWin_SampleDemo project.I`m use IAR EWARM ver 9.xx but in stm32cubeh7-v1-12-1 andSTM32Cube_FW_H7_V1.11.0\Repository\STM32Cube_FW_H7_V1.11.0\Projects\STM32H743I-EVAL\Demonstrations\STemWini find STemWin.ewp project which use OGLastSavedByProductVersion 8.20.2.14834.It mean`s STemWin.ewp should compile on EWARM 8.20 or late.Is it possible to use example on later version EWARM ?Best regards.

Hello,Where can i find the sources for MX66UW1G45G_STM32N6570-DK-OBL.bin and MX66UW1G45G_STM32N6570-DK.bin? The stm32-external-loader repository does not seem to have these?Thanks!

I want to generate an SBOM (Software Bill of Materials) for my STM32 firmware project, specifically targeting the STM32H733 microcontroller. I have tried searching for guides or examples of how others have done this for similar projects, but I haven’t been able to find any detailed resources. Any guidance or references on generating an SBOM for my firmware project would be greatly appreciated.

Hello,I have STM32F7 controller, using Free RTOS, trying to interface external NOR flash, S29GL128S10TFIV13.So at first, I was trying to do normal read/write operation, but here what I observed,void FMC_Init() { hnor2.Instance = FMC_NORSRAM_DEVICE; hnor2.Extended = FMC_NORSRAM_EXTENDED_DEVICE; /* hnor2.Init */ hnor2.Init.NSBank = FMC_NORSRAM_BANK2; hnor2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; hnor2.Init.MemoryType = FMC_MEMORY_TYPE_NOR; hnor2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16; hnor2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; hnor2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; hnor2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; hnor2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; hnor2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; hnor2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; hnor2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; hnor2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; hnor2.Init.Continuo

I have a dual core application running on an STM32H7 where I would like: the CM7 to tell the CM4 to enter stop modehave the CM4 enter stop modeat a later time, have the CM7 wake the CM4 from said stop modeIn the CM4 code, I'm doing this: HAL_PWREx_ClearPendingEvent(); HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFE, PWR_D2_DOMAIN);The problem is that HAL_PWREx_EnterSTOPMode is immediately exiting. I use the HSEM library for synchronizing all communication between the CM7 and CM4. I thought that maybe I had a case where the CM7 was notifying the CM4 via the HSEM library when I didn't want it to, causing it to wake. So as a test, I added an infinite loopwhile (1);after notifying the CM4 so that the CM7 wouldn't execute anything else. I know that debugging can/will wake the core. To confirm that the CM4 was getting the notification and calling the above HAL_PWREx code, I turn on an LED, delay for 5 seconds, then make the calls. After the enter function returns,

I am using STM32H743 controller, LAN8720 Ethernet chip, and Keil5 programming softwareI am using the IAP function of the network port and need to write the received data to FLASH. I found that the data read at that address after writing was modified. I found during debugging that after the "netif_add" function in LWIP initialization was executed, the data of my flash address was modified. May I ask what happened.Here is my MPU configuration, I'm not sure if it's related to MPU configuration   uint8_t MPU_Set_Protection(uint32_t baseaddr, uint32_t size, uint32_t rnum, uint8_t ap, uint8_t sen, uint8_t cen, uint8_t ben) { MPU_Region_InitTypeDef MPU_Initure; HAL_MPU_Disable(); // 配置MPU之前先关闭MPU,配置完成以后在使能MPU MPU_Initure.Enable = MPU_REGION_ENABLE; // 使能该保护区域 MPU_Initure.Number = rnum; // 设置保护区域 MPU_Initure.BaseAddress = baseaddr; // 设置基址 MPU_Initure.Size = size; // 设置保护区域大小 MPU_Initure.SubRegionDisable = 0X00; // 禁止子区域 MPU_Initure.TypeExtField = MPU_TEX_LEVEL0; // 设置类型扩展域为lev

Hi ST Community, I'm wondering if there's a sample project for a UART Bootloader for the NUCLEO-H755ZI-Q series. Thanks for your support  

tl;dr - HAL_UART_Receive_XXX, HAL_UART_Transmit_XXX == happiness; HAL_UART_Transmit_XXX, HAL_UART_Receive_XXX == misery.  The call to HAL_UART_Receive_XXX causes the transmission started by HAL_UART_Transmit_XXX to stall in both interrupt and DMA modes.Longer story:This affects both interrupt-driven and DMA operation, which is why I've added the DMA label.I am using FreeRTOS, and implementing a serial protocol that, while practically half-duplex in behavior, is written in a full-duplex form.  What I mean is the protocol doesn't really expect both sides to be transmitting at the same time, but the code isn't written to prevent it.  Theoretically parts of the protocol could overlap.The typical behavior for a transmission is to first call HAL_UART_Receive_DMA(..) to prime the receiver for a response, and then call HAL_UART_Transmit_DMA(..) to send a message.When the calls occur in that order, everything works perfectly.Unfortunately, sometimes the task responsible for