STM32 MCUs Embedded software

Im trying to use the HAL_Delay function but it seems like to code does not get passed this function. I have no clue what to even check to figure out what the problem is. I have attached the main fail to this post.

Hello STM community, I am currently working on a project that involves connecting a PS5 controller to an STM32 microcontroller. I would like to inquire about the feasibility and potential approaches for achieving this integration. Specifically, I am interested in: Whether the STM32 microcontroller supports USB host mode and is capable of communicating with USB HID (Human Interface Device) peripherals such as the PS5 controller.Any available libraries, examples, or resources that could help with implementing USB host communication and interfacing with the PS5 controller on the STM32 platform.Any considerations or challenges to be aware of when connecting and communicating with the PS5 controller, such as protocol compatibility, power requirements, and data handling.If anyone has experience or insights regarding this topic, I would greatly appreciate your input and guidance. Thank you in advance for your assistance. Best regards,Hirani Bhavik.

Hi,hope you doing good.We are currently using NUCLEO-L412RB-P along with X-NUCLEO-60K1A1 for testing. We are attempting to perform USB tunneling with the following sequence:1.NUCLEO-L412RB-P is connected to X-NUCLEO-60K1A12. X-NUCLEO-60L1A1 part and peripheral lines are connected to NUCLEO-L412RB-P.3.X-NUCLEO-60R1A1 part of board is powered up.4.A pen drive like device is connected to the X-NUCLEO-60R1A1 part of board.We tried debugging the sequence for USB TUNNELING using the example code, however we are unable to achieve the expected result.could you please give us resolving for this issue?Thank you.

I'm developing the STM32H735ZG using IAR EW.I wanted to design sectors 4-7 of the STM32H735ZG's flash memory as a readable/writable data storage area, so I created it by referring to the reference manual, but I can't read or write data properly. I modified the .icf file as attached, defining sectors 4-7 (0x08080000-0x080fffff) as the data storage area(named MEMORY block)./*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF; define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF; define symbol __ICFEDIT

Good day everyone!We are working with a custom PCB based on the STM32H750 Discovery board. We are trying to replace the existing MT25QL512ABB8ESF dual-bank setup with a dual S25FL512S setup (both driven with the same chip select).I've got a board with the replacement S25FL512S ICs soldered on and am following the ST MOOC on QSPI flash loaders, but I'm running into issues in passing the recommended testing script; it fails at the memcmp function. As per the ST course, I created an empty project, set up the ioc file, and copy-pasted the user code section to the appropriate commented regions in the generated qspi c and h files from the repo, and I used the provided code from stm32-external-loader/QSPI_Drivers/MT25QL512/quadspi.h at contrib · STMicroelectronics/stm32-external-loader · GitHub .I've reduced the SECTORS_COUNT to 3 for quicker debugging, commented out the MPU_Config function for now, and am watching the contents of a smaller buffer after calling the CS

Hi ST Community,I'm facing an issue with FatFs on SDMMC where f_open() or even f_mount() returns FR_DISK_ERR, even though the SD card is initializing correctly at the HAL level.Here's a summary of the problem and what I’ve verified so far.HAL_SD_Init() completes successfullyCard information is read correctly:CIDCSDRCACapacity (LogBlockNbr, LogBlockSize)SDMMC interface appears operationalRaw HAL read/write tests (CID/CSD) work fineI would be grateful if ST experts or anyone familiar with SDMMC + FatFs integration please help me to resolve this issue : 

Typo fixed in title - was "Helliun" I'm developing a project that will heavily utilize DSP for audio processing, including neural networks. However, I'm having difficulties with the DSP; I haven't finished reading all the documentation yet. I even consulted Claude Opus on the process and other AI resources, but they all point to a non-existent path, which would be to install CMSIS-DSP via CubeMX in the ARM software tree. Is anything else needed for DSP use? Taking advantage of this post, how should I access the board's internal microphone? Are there any code examples besides STM32N6-GettingStarted-Audio, or is that the best example to learn how to handle the microphone that comes with the board? Thank you for your help.

I have an XCore407I board with an Ethernet port installed. I'm trying to create a simple UDP server in Stm32CubeIDE. Compilation and uploading to the board is OK. But the board doesn't respond to ping and isn't visible in the router's device list.Here are my settings in IDE.Spoiler (Highlight to read)Here is the main code.int main(void) { HAL_Init(); SystemClock_Config(); /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_LWIP_Init(); // Udp init function udpServer_init(); while (1) { MX_LWIP_Process(); } }Unfortunately, I can't attach the entire project here. But I can add code from other modules upon request.Can you tell me how to set this up correctly so it works? Thank you.

Hi everyone, I’m asking for your help with accessing my SD card. I’m running into an issue with the STM32N6DK750 Discovery Kit and would really appreciate some advice. I’m trying to write data to an SD card using FileX and ThreadX. Everything compiles and debugs fine, but nothing actually gets written to the card. I also tried the FX_MultipleAccess example provided by ST, but it doesn’t compile. I’ve tried fixing several compilation errors, but some declarations are missing, like byte_pool in app_filex.c. I’m not sure what’s causing the issue, and I’m wondering if I might have missed an important step or misconfigured something.

Hi,I'm developing a camera interfacing application. I've used GPDMA in linear-circular mode. But, now I have to handle larger resolution(640x480). Is there any application example from where I can start configuring DMA in CubeMx?

Hello,I'm using uSD.I observe that in the sd_diskio.c driver SD_TIMEOUT is 30sec, is'nt very long ?If uSD works normally is not sufficient just 1sec ? Best regards. 

Following this thread Solved: USBPD EPR Source - STMicroelectronics Community Do you have a similar guide on how to do EPR as a Sink?

Hi here. I am trying to get  STM32H743iit as usb_audio_device with CubeMX latest version.No initialization of stm32 sound device in windows 10 device manager.Other projects from this link  https://www.waveshare.com/wiki/OpenH743I-C  especially USB_FS, USB_HS working good, but in windows devise manager  no descriptors info in usb device properties windows for HID project. Could somebody help where i am got problem with usb_audio_device? I change VID, heap size but it is do not help. Please help.Regards

I'm trying to interface a TI ADC with an STM32U575ZI or STMU545RE (same issue on both Nucleo boards).The ADC has a "data ready" pin that needs to trigger a fixed-size transfer of 32bytes over SPI.  Given the overall sampling rate, only a few microseconds are available for overhead.  Seems like a natural fit for the autonomous mode + DMA features on the STM32U micros, but I can't seem to figure out how this is supposed to go together.I can get one transfer going no problem, sometimes two, but something always errors out.  Currently getting a MODF flag, which makes no sense based on the documentation as the NSS system is set to "software" and always at 1.Is there a document describing how the DMA and SPI modules interact under autonomous mode?  I'm clearly missing something important here.  Handshaking, what causes the TSIZE to reload the CTSIZE register, recommended DMA configs + trigger setups, anything?Working on putting together an example for people to disse

Found a bug with RX_POOL buffers been permanently used. There are total of 12 buffers defined by default. Adding more buffers will prolong the operation, but eventually all of them will be permanently locked. Using the latest available from ST LWIP stack. Our configuration: enabled ARP, ICMP; TCP server with 5 available connections. As soon as a whole buffers are locked, the ethernet driver won't process any incoming packets. Soon after start the number of used buffers goes from 0 to 4 with no active TCP or UDP communication, just a normal network activity. Once TCP communication is started, and if there is no traffic congestion like opening several connections at the same time or sending too many packets, LWIP may function without a problem for days, which makes finding the issue with losing the ethernet communication difficult. The number of available buffers may go down one-by-one. Opening several connections simultaneously and starting the traffic on all of them locks the buffers i

Hi everyone,I’m building a coffee machine project using STM32C071 (C0) mainly because it has USB. I need USB Host MSC to:Mount a USB flash drive (FAT)Read/write files (params/logs)Firmware update from USB driveThe “official” ST stack seems to be ThreadX + USBX + FileX. Since there’s no USB Host MSC example for C0, I used an STM32L4R5 example (much larger RAM) as reference and adapted it.Issue: To pass ThreadX/USBX init, I kept increasing stacks/pools until I’m using ~20 kB of RAM. Then, when I plug the flash drive, enumeration fails with out-of-memory errors (e.g., UX_DEVICE_ENUMERATION_FAILURE / allocation failure).Questions:Is ~20 kB RAM just to init (and still fail at enumeration) expected for USBX Host MSC + FileX, or does it strongly suggest misconfiguration?Is there any official guideline/table (ST/Azure RTOS) for typical/minimum RAM for USBX Host + MSC + FileX (FAT)?Is there a practical RAM “floor” to enumerate + mount FAT + read/write files (single device, no HUB)? Like “below

I am working with a custom board that uses the STM32H7S38T chip. I am trying to use the SPI flash example from Zephyr to write to and read from the BY25Q16ES NOR flash. I am using the XSPI interface in normal SPI mode. I can read out the JEDEC ID (0x9F) as 0x684015, which matches the value given in the datasheet.   When reading the SFDP (0x5A), the MISO is pulled high after the dummy cycles. Have I overlooked something? The flash datasheet clearly states that the SFDP is available. Zephyr Debug output: ------------------------------------- [00:00:00.000,000] <dbg> flash_stm32h7: stm32h7_flash_init: Flash initialized. BS: 32[00:00:00.000,000] <dbg> flash_stm32h7: stm32h7_flash_init: Block 0: bs: 8192 count: 8[00:00:00.000,000] <dbg> flash_stm32_xspi: flash_stm32_xspi_init: XSPI Init'd[00:00:00.100,000] <dbg> flash_stm32_xspi: flash_stm32_xspi_init: Reset Mem (SPI/STR)[00:00:00.100,000] <dbg> flash_stm32_xspi: HAL_XSPI_StatusMatchCallback: Status Matc

Hi all,I’m running into an issue with LPTIM1 when using LSE as the clock source. The exact same configuration works perfectly when I use LSI or PCLK, but with LSE the code gets stuck waiting for the ARROK flag after writing ARR.The code blocks forever at:while (!LL_LPTIM_IsActiveFlag_ARROK(LPTIM1)) {} So it looks like the ARR register update is never acknowledged when LSE is the clock.Important notesLSE is definitely running — it’s already used elsewhere in the system without issues.We are looking for low power applicationwe using STM32U073CBT6Clock configurationLL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_LSE); LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1); LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOC); NVIC_SetPriority(TIM6_DAC_LPTIM1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 3, 0)); NVIC_EnableIRQ(TIM6_DAC_LPTIM1_IRQn);LPTIM configuration/* Make sure timer is disabled before config */ LL_LPTIM_Disable(LPTIM1); /* Select clock & prescaler FIRST *

I referred to this article: “Bootloader jump to Application HardFault - STM32H563.”I am also using the STM32H563, and used the following function to jump to the application, but the jump does not succeed. My test program is very simple. After creating an STM32H563 project, I only configured the UART to print messages so I can identify which program is currently running./* Bootloader */ typedef void (*pFunction)(void); void relocate_exe(uint32_t app_addr) { uint32_t appStack; uint32_t appResetHandler; pFunction appEntry; appStack = *(volatile uint32_t *)app_addr; appResetHandler = *(volatile uint32_t *)(app_addr + 4); appEntry = (pFunction) appResetHandler; __disable_irq(); SysTick->CTRL = 0; SysTick->LOAD = 0; SysTick->VAL = 0; SCB->VTOR = (uint32_t) app_addr; __set_MSP(appStack); //__enable_irq(); appEntry(); } int main(void) { HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_USART3_UART_Init(); char msg[128]; sprintf(msg, "Bootloader!!!(%x)\

  Hello everyone, I am facing a confusing behavior with USB SOF events on two identical STM32 boards and I would appreciate any insight. Hardware 2 × NUCLEO-H743ZI2 Same MCU revision (checked device ID, revision ID – identical) Same USB connection to the same PC (USB OTG FS, device mode) Software Exactly the same firmware binary programmed on both boards STM32 HAL + CubeMX generated project USB CDC device (USB OTG FS) No conditional compilation, no board-specific code What I want to measure I wanted to check: Whether USB SOF events are really occurring every 1 ms Whether SOF can be considered a reliable timing source So I implemented a very simple counter in the SOF callback: #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif { sof_eventc++; USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); } Additionally: TIM2 is configured as a 1 Hz timer In t

Hi team,I am working on the STM32U585I-IOT02A board and trying to implement USB dual-role functionality (Host + Device).My goal is:USB Host: MSC class (to read firmware from a USB flash drive)USB Device: CDC class (for communication with a PC)I have enabled both the USB Host stack and USB Device stack in CubeMX, but I am unable to get the dual-role setup working reliably.My main objective is to upgrade firmware using a USB flash drive (MSC Host) while still supporting CDC Device communication.I would like to know:Does STM32U5 support USB dual-role operation (Host + Device) simultaneously or via role switching?Is there any example project or reference implementation for USB dual-role on STM32U5?Are there recommended approaches for implementing firmware upgrade via USB MSC Host on this board?Any guidance or example projects would be very helpful.Thank you.

I have an STM32H7A3ZIT running at 280MHz with 4 SPI buses attempting to “simultaneously” communicate with external ADCs. All 4 SPI are set up as full-duplex masters, 16-bit data size, 8.75 MHz clock speed, and software chip select.I’m using the HAL function HAL_SPI_TransmitReceive_IT to sequentially initiate the data transfer for each SPI bus. I expected each transfer to start quickly one after another, but instead I’m finding large time gaps. The TransmitReceive_IT composite image below shows the chip select line (yellow) and the SPI clock signals (cyan) for each sequential SPI bus. You can see the first 2 buses start clocking quickly, but then there is a time gap before the third and fourth buses start clocking. The code functionally works as the received data is correct, but the end of the transfer for the fourth SPI bus is too close to the next CS transaction, not leaving a lot of time for data processing.TransmitReceive_ITOddly enough, if I change the function to just receivi

Hi,I want to fly the STM32F429I-DISC with the 8 MB SDRAM. I use CubeIDE and selected the right board. All units are set to default. I commented out everything that had to do with os.With help of ChatGPT I hacked together an initialization of the SDRAM and set up a SDRAM Test. That seems to work partly but with weird effects. In the following code: start/end 0x00/0xff or 0x100/0x1ff works fine, but start/end 0x00/0x101 reads out 0x100 at  address 0x0. Maybe it is an timing issue with precharged lines.THXCheersDetlef #define SDRAM_BASE_ADDR ((uint32_t)0xD0000000) void SDRAM_Test(void) { volatile uint16_t *p = (volatile uint16_t *)SDRAM_BASE_ADDR; uint32_t i ; uint32_t start = 0x100 ; uint32_t end = 0x302 ; for (i=start; i<end; i++) p[i] = i; sprintf(buf,"start \r\n",i); HAL_UART_Transmit(&huart1, (uint8_t *) buf, strlen(buf), HAL_MAX_DELAY); while(1){ for (i=start; i<end;i++) if (p[i] != i){ sprintf(buf,"no 0x%x 0x%x\r\n",i,p[i]); HAL_UART_Transmit(&

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Hello everyone,I am currently working on a project to develop drivers for STM32F4 microcontrollers, based on Reference Manual RM0090 (without HAL, only CMSIS and register access).The goal of the project is to design reusable low-level drivers for the following peripherals:USART / UARTSPII2CI am now in the code implementation phase.I would like the community's help with the following:Examples of source code or references (preferably bare-metal / register level) for:SPI : transmission et réceptionI2C : master transmit / master receiveUART : transmission et réceptionRecommendations on API structure and function naming, for example:SPI_Init(), SPI_Transmit(), SPI_Receive()I2C_MasterTransmit(), I2C_MasterReceive()USART_Transmit(), USART_Receive()Any help, code snippets, links to reference implementations, or feedback would be greatly appreciated.Thank you in advance for your help.Best regards, *This post has been translated from French to comply with the ST Community guidelines.