stm32h743 SPI erratum implemented in HAL?

[Alex_001]

Hi Team,

Could you please confirm whether the following SPI erratum is considered in HAL version 1.11? I am currently using an MCU with revision V.

[Andrew Neil]

I don't think that HAL generally works around errata? - see this recent post by @TDK 

[Alex_001]

Thanks @Andrew Neil for your reply.

This below code snippet is from HAL and you can see that interrupts are disabled after the spi is disabled. Is this correct according to errata 2.22.4 ? The wrokaround says 

"Keep TXP and TXC (the latter if the TSIZE field contains zero value) interrupt disabled whenever the SPI

peripheral is disabled"

 

static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
{
 /* Disable SPI peripheral */
 __HAL_SPI_DISABLE(hspi);

 /* Disable ITs */
 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
 SPI_IT_FRE | SPI_IT_MODF));

 /* Clear the Status flags in the SR register */
 __HAL_SPI_CLEAR_EOTFLAG(hspi);
 __HAL_SPI_CLEAR_TXTFFLAG(hspi);

 

[Saket_Om]

Hello @Alex_001 

The errata sheet serves as the definitive reference for all silicon limitations and their workarounds. Not every erratum is implemented within the HAL because:

• Many workarounds are application‑dependent (they depend on how the peripheral is used, timing, power modes, etc.), so HAL cannot safely apply them for everyone.

• Some workarounds would change performance or behavior of existing applications if they were always enabled (extra delays, dummy accesses, disabled features…).

[Andrew Neil]

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@Saket_Om wrote:

Not every erratum is implemented within the HAL 

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This suggests that some errata are implemented within the HAL ?

 

PS:

I guess another problem with implementing errata workarounds in the HAL is that the HAL would then need to know the specific chip revision - to know whether or not the erratum applies.

[mƎALLEm]

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@Andrew Neil wrote:

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This suggests that some errata are implemented within the HAL ?

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In some cases yes.

Example:  the errata: 2.2.10 Reading from AXI SRAM may lead to data read corruption (from ES0392 - Rev 15) on STM32H7x3 rev Y:

The workaround was implemented in system_stm32h7xx.c:

 /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
 if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
 {
 /* if stm32h7 revY*/
 /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
 *((__IO uint32_t*)0x51008108) = 0x00000001U;
 }