STM32N6 SPI5 + GPDMA TX: MOSI stays low, CPU TX works
- April 1, 2026
- 2 replies
- 156 views
Hello,
I am testing SPI5 TX by GPDMA on an STM32N6 device and I found behavior that seems inconsistent with the reference manual.
MCU / Environment
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MCU: STM32N647X0H
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Toolchain: STM32CubeIDE 2.1.1
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CubeMX / CubeN6 version: STM32Cube_FW_N6_V1.3.0
Issue summary
I configured SPI5 as:
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Master
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Simplex TX-only
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Software NSS
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SSI set high
I configured GPDMA1 Channel0 as:
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Memory-to-peripheral
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Source = TX buffer
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Destination = SPI5->TXDR
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Transfer length = 8 bytes
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TX pattern = A5 5A A5 5A A5 5A A5 5A
Observed behavior
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If I write data directly to SPI5->TXDR by CPU, MOSI outputs correctly.
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If I use GPDMA for SPI5 TX, SCK may appear, but MOSI stays low / no valid TX data is output.
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I reduced the project to a minimal LL test case and the behavior is reproducible.
What I already verified
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Same SPI5 pin configuration is used in both tests.
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CPU TX path works with the same SPI configuration.
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TX buffer content is correct in memory (A5 5A ...).
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DMA source address points to the TX buffer.
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DMA destination address points to SPI5->TXDR.
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DCache is disabled during this test.
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I also tested simplex TX-only to reduce variables.
Expectation
According to RM0486, SPI TX DMA requests should be generated when TXP is set, and DMA should write data into SPI_TXDR.
Question
Could ST please confirm:
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whether this is an expected limitation on STM32N6 SPI5 + GPDMA,
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whether there is any required configuration not mentioned clearly in RM / Cube-generated code,
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or whether this may be a silicon / HAL / LL issue?
Additional information
I can provide:
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minimal project
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register dump
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oscilloscope screenshots
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CPU TX working waveform vs DMA TX failing waveform
The attached file is the compressed project archive for this minimal test case.
Thank you.