Solved
Why is AXI RAM and RIF necessary when using DCMIPP?
Hello, i just wanna take a snapshot by STM32N6570-DK with IMX335. I am using SnapshotDecimation as my reference. after reviewing the code. i wonder why AXI RAM3/4 and RIF are necessary for this project i saw it in 'HAL_DCMIPP_MspInit' function, but i didnt found anything about AXI RAM in other parts of the code.
anyone can explain why does axiram necessary for this project?
void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef* hdcmipp)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
RAMCFG_HandleTypeDef hramcfg = {0};
RIMC_MasterConfig_t RIMC_master = {0};
if(hdcmipp->Instance==DCMIPP)
{
/* USER CODE BEGIN DCMIPP_MspInit 0 */
/*** Enable peripheral clock ***/
/* Enable DCMIPP clock */
__HAL_RCC_DCMIPP_CLK_ENABLE();
__HAL_RCC_DCMIPP_FORCE_RESET();
__HAL_RCC_DCMIPP_RELEASE_RESET();
/*** Configure the NVIC for DCMIPP ***/
/* NVIC configuration for DCMIPP transfer complete interrupt */
HAL_NVIC_SetPriority(DCMIPP_IRQn, 0x07, 0);
HAL_NVIC_EnableIRQ(DCMIPP_IRQn);
/*** Enable peripheral clock ***/
/* Enable CSI clock */
__HAL_RCC_CSI_CLK_ENABLE();
__HAL_RCC_CSI_FORCE_RESET();
__HAL_RCC_CSI_RELEASE_RESET();
/*** Configure the NVIC for CSI ***/
/* NVIC configuration for CSI transfer complete interrupt */
HAL_NVIC_SetPriority(CSI_IRQn, 0x07, 0);
HAL_NVIC_EnableIRQ(CSI_IRQn);
/* USER CODE END DCMIPP_MspInit 0 */
/* USER CODE BEGIN DCMIPP_MspInit 1 */
/* DCMIPP Clock Config */
/* DCMIPP clock configuration */
/* Typical PCLK is 333 MHz so the PLL1 is configured to provide this clock */
/* Configure DCMIPP clock to IC17 with PLL1 */
/* PLL1_VCO Input = HSI_VALUE/PLLM = 64 Mhz / 4 = 16 */
/* PLL1_VCO Output = PLL3_VCO Input * PLLN = 16 Mhz * 75 = 1200 */
/* PLLLCDCLK = PLL3_VCO Output/(PLLP1 * PLLP2) = 1200/4 = 300Mhz */
/* DCMIPP clock frequency = PLLLCDCLK = 300 Mhz */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_DCMIPP;
PeriphClkInitStruct.DcmippClockSelection = RCC_DCMIPPCLKSOURCE_IC17;
PeriphClkInitStruct.ICSelection[RCC_IC17].ClockSelection = RCC_ICCLKSOURCE_PLL1;
PeriphClkInitStruct.ICSelection[RCC_IC17].ClockDivider = 4;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CSI;
PeriphClkInitStruct.ICSelection[RCC_IC18].ClockSelection = RCC_ICCLKSOURCE_PLL1;
PeriphClkInitStruct.ICSelection[RCC_IC18].ClockDivider = 60;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* IMX335 Sensor HW Reset */
/* Enable GPIO clocks */
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
GPIO_InitTypeDef gpio_init_structure = {0};
/* Initialize camera NRST pin */
gpio_init_structure.Pin = GPIO_PIN_8;
gpio_init_structure.Pull = GPIO_NOPULL;
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
/* Initialize camera EN pin */
gpio_init_structure.Pin = GPIO_PIN_2;
gpio_init_structure.Pull = GPIO_NOPULL;
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
/* Camera sensor Power-On sequence */
/* Assert the camera Enable and NRST pins */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_8, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_RESET);
HAL_Delay(200); /* NRST and Enable signals asserted during 200ms */
/* De-assert the camera STANDBY pin (active high) */
HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET);
HAL_Delay(3); /* NRST de-asserted during 3ms */
/* SRAM3 and SRAM4 memories clock enable */
LL_MEM_EnableClock(LL_MEM_AXISRAM3);
LL_MEM_EnableClock(LL_MEM_AXISRAM4);
/* Power On AXSRAM3 and AXISRAM4 */
hramcfg.Instance = RAMCFG_SRAM3_AXI;
HAL_RAMCFG_EnableAXISRAM(&hramcfg);
hramcfg.Instance = RAMCFG_SRAM4_AXI;
HAL_RAMCFG_EnableAXISRAM(&hramcfg);
__HAL_RCC_RIFSC_CLK_ENABLE();
RIMC_master.MasterCID = RIF_CID_1;
RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_DCMIPP, &RIMC_master);
HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_DCMIPP , RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
/* USER CODE END DCMIPP_MspInit 1 */
}
}
