SPI Multi Device Bus Design and Driver Capability Evaluation

[Chris_Hua]

Hi 

      I hope you are well.

Background: The SPI bus of MCU has 9 slave devices, with loads of 1pcs x C component, 2pcs x A component, and 6 pcs x B component. The SPI rate of component is 200kbps, the SPI rate of A component is 1Mbps, and the SPI rate of C component is 100kbps. The SPI waveform has ringing, and the SPI communication between C component and  A component sometimes reports errors.
Request for support: Can you provide SPI multi device bus design materials to evaluate whether MCU can drive multiple SPI slave devices, whether the number of SPI slave devices is reasonable, and whether the capacitive load of slave devices is reasonable?

[KnarfB]

I doubt that there is specific material covering your use case.

General information about the IO driving capabilities are in the data sheet of your MCU.

If your EDA toolchain supports it, you may inspect the IBIS models provided in the CAD ressources tab of the product web site and use that in simulations.

You may vary the IO pin speed setting (influencing the driver strength).

hth

KnarfB 

[TDK]

It shouldn't be a problem if you are only going up to 1 MHz and these are standard SPI slave devices.

Put a logic analyzer on the line to see the signal integrity. Probably you're getting cross-talk or other interference. Ensure components are not too far away from each other.