If pullup is enabled on gpio for SPI Clock, does pullup have any effect while spi is enabled?

[AMacd.1]

Say I am operating as master with CPOL=1.  Because the NSS pin seems to lag the enable bit (SPE) slightly, my logic analyzer always barfs on the first SPI packet because the clock is in the wrong state.

So, I set the GPIO to have a pullup on the clock in CubeMX and the problem goes away - as soon as the init functions run, the clock goes high and stays that way until the first SPI transmit.  Also, the clock stays high after the end of the transfer if the SPI is disabled in the callback function.

My only concern is for power consumption: It is obvious that the pullup gets applied when the SPI is disabled but I don't know is if the pullup applied all the time even when the alternate mode of the GPIO is set, i.e. is the pullup still applied at the pin when the SPI is enabled?  Do clock pulses during an SPI transaction work against the pullup?

 

[TDK]

Yes, it's still applied and will pull extra current while the pin is driven low.

You can enable the peripheral before sending the first transaction which will set SCK to the correct value. Doing a transaction with CS kept high will also do this.

[AMacd.1]

Thanks @TDK, so do you mean doing something like this?

void Spi2Tx(const uint8_t *Buffer, size_t Len)
{
 TransferState = TransferWait;
 __HAL_SPI_ENABLE(&hspi2);
 HAL_GPIO_WritePin(NSS_GPIO_Port, NSS_Pin, GPIO_PIN_RESET);
 if(HAL_SPI_Transmit_DMA(&hspi2, Buffer, Len) != HAL_OK)
 {
 Error_Handler();
 }

 while (TransferState == TransferWait)
 {
 }

 switch(TransferState)
 {
 case TransferComplete :
 break;
 default :
 Error_Handler();
 break;
 }
}

void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
 HAL_GPIO_WritePin(NSS_GPIO_Port, NSS_Pin, GPIO_PIN_SET);
 __HAL_SPI_DISABLE(hspi);
 TransferState = TransferComplete;
}

However, I don't understand what you mean by "Doing a transaction with CS kept high will also do this."  Can you please elaborate?  Is CS == NSS?  What does this pin have to do with the SPI peripheral when using software control of NSS (i.e. SSM=1)?

Edit: add missing initialization of TransferState

Edit 2: Changed question about "CS kept high."

[TDK]

You should put a delay between enabling the peripheral (which sets SCK to the correct value) and the first transaction. Typically there is a timing requirement here.

> However, I don't understand what you mean by "Doing a transaction with CS kept high will also do this."  How can I do that when the GPIO Mode for the clock pin is set to alternate function in CubeMX?

You are controlling CS, so do a transaction without setting it low. CS and NSS refer to the same pin. Presumably you set it high during pin initialization.

uint8_t data = 0;
HAL_SPI_Transmit(&hspi2, &data, 1, HAL_MAX_DELAY);