Power On-Off sequence for STM32N657X0H3Q

[kadam]

Hello Team,

We are using the internal SMPS configuration for the core power supply. However, the power-up sequence does not specify the timing requirements for the different stages.

Could you please provide the timing details for the following?

 

• What should be the time duration for the PWR_ON signal to transition from low to high while VDD and VDDA18AON are rising (Step 1)?
• After PWR_ON goes high, what is the required time duration for VDDA18PMU / VDDSMPS to rise (Step 2)?
• What is the exact meaning and function of the SDEN signal?
• Are there any additional considerations or recommended guidelines to be followed during the power-up and power-down sequence?

 

Thanks

 

[FBL]

Hello @kadam 

1. Based on AN5967, once VDD and VDDA18AON are above the POR threshold, the external voltage regulator providing VDDA18PMU and VDDSMPS supplies is enabled via the PWR_ON signal.

• VDDA18PMU / VDDSMPS must rise after PWR_ON has enabled the external regulator.
• SDEN is used to enable or disable the SMPS path.

I hope it's clear

[kadam]

Hello FBL,

Thank you for your suggestion.

In our custom board design, we are using only one regulator to generate 1.8V.

Could you please suggest us which power tree will be suitable to manage power up sequence?

Option-1

Option-2

Option-3

 

Regards,

Kadam