Question on 4.7uF ceramic capacitor

[AA4]

Post edited by ST moderator: title and post edited to translate the content.

我在stm32F412RGT6的数据手册的6.1.6部分看到关于滤波电容的描述，2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.从图中来看是以144PIN的芯片为例，但我使用的是64PIN的封装，是否也需要在其中一个VDD引脚放置4.7uf的电容，如果需要，是单独放置一个4.7uf还是与一个0.1uf并联放置

Translation:

"In section 6.1.6 of the STM32F412RGT6 datasheet, regarding filter capacitors, it states: "2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pins." The diagram shows this for a 144-pin chip, but I'm using a 64-pin package. Do I also need to place a 4.7 µF capacitor on one of the VDD pins? If so, should I place a single 4.7 µF capacitor or connect it in parallel with a 0.1 µF capacitor?"

[AScha.3]

अहं चीनीभाषां पठितुं न शक्नोमि...

...so write in english , please.

[AA4]

I found the description about the filter capacitor in Section 6.1.6 of the data sheet for STM32F412RGT6. 2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pins. From the figure, it is assumed that the 144PIN chip is used as an example. However, I am using a 64PIN package. Does it also need to place a 4.7uf capacitor at one of the VDD pins? If so, should it be placed separately as a 4.7uf capacitor or in parallel with a 0.1uf capacitor?

[mƎALLEm]

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@AA4 wrote:

However, I am using a 64PIN package. Does it also need to place a 4.7uf capacitor at one of the VDD pins? If so, should it be placed separately as a 4.7uf capacitor or in parallel with a 0.1uf capacitor?

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In parallel to the VDD power supply ring near to the MCU + in parallel to each 100nF connected to each VDD pin. No matter the package used.