STM32N6 Bootrom clock configuration

[ZainNoman]

In the document UM3234 we see the following description of clock configuration

On my Nucleo board, I haven't blown any fuses and measured a clock frequency of 32 MHz. Since the XSPI is configured to have a prescaler of 2 by BOOTROM (also mentioned in UM3234), this implies that the board is using the default clock scenario. The document also mentions this regarding the nominal scenario.

"During secure boot, the boot ROM sets up PLL1 to switch to CM55, APB, AHB, and AXI clocking at the nominal
boot frequency"

Does this mean that if i dont have secure boot enabled yet, ill get the default clock, and as soon as I enable secure boot my clock frequency will increase to 400 MHz?. 

[NesrynELMK]

Hello @ZainNoman 

 

If the fuse configuration is left at its default value and the measured CPU frequency is $32\text{MHz}$, the device is running from the HSI clock source. In this case, the device is not in secure boot mode; it is operating in development boot mode.

In development boot mode, the CPU PLL is never enabled, regardless of the no_cpu_pll fuse setting.

When secure boot mode is selected (flash boot or serial boot), the CPU frequency is determined by the no_cpu_pll fuse:

• no_cpu_pll = 0: nominal CPU clock $400\text{MHz}$ (PLL enabled).
• no_cpu_pll = 1: CPU clock $64\text{MHz}$ (HSI).

"Does this mean that if i dont have secure boot enabled yet, ill get the default clock," 

This depends on what is meant by “secure boot mode is not enabled.” If it refers to the boot pin selection being set to development boot mode, then yes: in this mode the PLL is not used and the HSI clock source is selected for the CPU.

 

 

Br,

[ZainNoman]

When i measured the 32MHz clock frequency, I had set the boot pins to flash boot mode. I measured the clock signal immediately after reset and my application in the flash doesn't use XSPI. So the 32Mhz clock signal should only be coming from the BootROM code.

So I needed a bit of clarity whether in flash boot mode, the nominal/default clock selection depends on only the no_pll_bit or also on the secure_boot bits in OTP18. If it doesn't depend on secure_boot then shouldn't i be getting 200Mhz.

[NesrynELMK]

 

Hello @ZainNoman 

By default, the Nominal mode is used by the BootROM because the no_cpu_pll bit = 0. The CPU clock is therefore 400 MHz.

However, in Table 25 the value per_ck = 400 MHz is incorrect for the Nominal column. It should be per_ck: hsi_ck = 64 MHz (same configuration in Nominal and Default) (fix planned for the end of April 2026).

Moreover, XSPI1_P2 is configured with a prescaler DIV2, so XSPI1 ultimately operates at a clock of 64/2 = 32 MHz.

 

Br,

 

[ZainNoman]

Thanks! that clears everything up. There is a typo in your response though where you entered 46 MHz instead of 64. One last thing i wanted to confirm was whether the SPI clock speed used by BootROM in flash boot is configurable at all. It looks like it isn't after your last answer but I just wanted to confirm. Again thanks for your thorough and timely response!

[NesrynELMK]

Hello @ZainNoman ,

 

I believe that you're referring to the XSPI clock.
The XSPI clock is fixed by the BootROM(=32MHz); it cannot be modified at this stage.
However, you can change it in your FSBL or in the application and drive it up to 200 MHz.

 

Br,