STM32N657 External RAM (S80KS5123GABHB020) Memory-Mapped Address Clarification

[siddum]

Hello ST Community Team,

We are currently working with the STM32N657X0H3Q1 device and using an external DRAM – S80KS5123GABHB020 (512 Mbit) connected via the XSPI interface.

We have successfully configured XSPI and external memory initialization (using CubeMX / HAL), and the external memory is intended to be used for TouchGFX frame buffers and application data.

However, we would like clarification on the following points:

1. What is the correct memory-mapped base address that should be used for the S80KS5123GABHB020 DSRAM on STM32N657X0H3Q1 ?

2. Is the memory accessed through the XSPI1  memory-mapped region, and what is the exact address range?

3. Are there any STM32N6-specific constraints or alignment requirements when using large external DSRAM (512 Mbit) for TouchGFX or heap allocation?

4. Is there any reference example or application note available for STM32N657 with external PSRAM configuration?

Currently, we are unsure at which address we should read/write the external DRAM, and accessing an incorrect address leads to HardFaults.

Any guidance or reference documentation would be very helpful.

Thank you for your support.

Best regards,

Marka.

[KDJEM.1]

Hello @siddum;

 

For addresses mapping, I recommend you to look at RM0486 Rev 3 Table 2. Memory map and peripheral register boundary addresses.

When configured in memory-mapped mode, the external SPI device is seen as an internal
memory. Note: No more than 256 Mbytes can be addressed even if the external device capacity is larger.

Also, I advise you to check 28.5 Address alignment and data number section in RM0486 Rev 3.

You can find in STM32CubeN6 firmware an XSPI_PSRAM_MemoryMapped example.

Thank you.

Kaouthar

[KDJEM.1]

Hello @siddum ;

 

Any update?

Is my reply answered your initial request?

 

Thank you.

Kaouthar 

[siddum]

Hello KDJEM.1,

We are currently working with the STM32N657X0H3Q device and interfacing an external S80KS5123GABHB020 (512 Mbit Octal SPI RAM, 64 MB) through XSPI1.

We are facing an issue where we are not able to reliably read or write data to the external RAM in memory-mapped mode. Additionally, when attempting to view the external memory region (0x90000000) in the debugger memory window, the debug session exits automatically.

Even after enabling memory-mapped mode, when we perform a simple test such as writing a value to the base address (0x90000000) and reading it back, the read value does not match the written value.

Our configuration details are as follows:

• XSPI1 configured in Octal SPI mode .

• Memory-mapped mode enabled.

• External RAM: S80KS5123GABHB020 (512 Mbit / 64 MB)

• Default XSPI1 base address: 0x90000000

We kindly request your guidance on the following points:

1. Are there specific read/write opcodes required for this memory in STR or DTR mode?

2. Is any special configuration of mode registers required before enabling memory-mapped mode?

3. What are the mandatory dummy cycle and latency settings for this device?

4. Is delay block calibration required on STM32N657 before accessing this memory?

5. Are there known limitations or additional MPU/cache configuration requirements for stable memory-mapped operation?

We have attached our XSPI configuration for reference.

Kindly suggest the correct initialization sequence and configuration required to achieve reliable read/write operation in memory-mapped mode.

Thank you for your support.

Best regards,
Marka

[KDJEM.1]

Hello @siddum ,

 

I think the initial questions are answered. For more visibility on these new question, I recommend you to create a new post.

Please don't ask many questions in the same thread. Please keep one question per thread.

 

Thank you for your understanding.

Kaouthar