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Terry Greeniaus
Senior
May 31, 2024
Solved

STM32U5 extended calibration procedure in RM0456 Rev 5 page 1269 is buggy

  • May 31, 2024
  • 4 replies
  • 1144 views

Hello,

I was trying to implement extended calibration for ADC1 on my STM32U575 according to RM0456 Rev 5.  I have a revision ID 0x3001 chip which should support extended calibration.  The chip would hang very badly (can no longer connect with debug probe!) after step 6 ("Set the LATCH_COEF bit").  I took a look at the HAL code in stm32u5xx_hal_adc_ex.c  and it is doing a few things differently:

  1. Using DMB instructions between setting CALINDEX and CALFACT and between setting CALFACT and setting LATCH_COEF.
  2. Preserving the low-order 8 bits of CALFACT when writing 0x03021100 to the register.

When I changed my code to do those two things the ADC now completes calibration properly and doesn't hang my debug connection.

It would be helpful if the RM could be updated accordingly!

Thanks,

TG

Best answer by KDJEM.1

Hello @Terry Greeniaus ,

 

Thank you for bringing this issue to our attention.

I reported internally.

The internal ticket 183050 (not accessible by community users) has been opened to confirm and fix the issue.

Thank you for your contribution in STCommunity.

 

Kaouthar

4 replies

KDJEM.1
KDJEM.1Best answer
Technical Moderator
May 31, 2024

Hello @Terry Greeniaus ,

 

Thank you for bringing this issue to our attention.

I reported internally.

The internal ticket 183050 (not accessible by community users) has been opened to confirm and fix the issue.

Thank you for your contribution in STCommunity.

 

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
Uwe Bonnes
Chief
January 28, 2026

Has there been any outcome of this issue and the RM is updated?

KDJEM.1
Technical Moderator
January 28, 2026

Hello @Uwe Bonnes ;

 

A new note is added in RM0456 rev 6: "The values written to the ADC_CR (CALINDEX[3:0] and ADCALLIN), ADC_CALFACT, and ADC_CALFACT2 registers are internally applied asynchronously from Fadc_ker_ck. As a result, consecutive fast accesses to these registers might generate errors. To prevent errors from occurring, the software can insert the __DMB(); command after each access to these registers."

 HAL driver is already took into account on this point.

KDJEM1_0-1769604247175.png

 

 

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
Terry Greeniaus
Senior
January 28, 2026

That doesn't seem to address my second point, which was preserving the low-order 8 bits of the CALFACT2 register.  This is what is happening in the HAL code:

 MODIFY_REG(hadc->Instance->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);

 

KDJEM.1
Technical Moderator
January 29, 2026

Hello @Terry Greeniaus ,

 

Thank you for the follow-up.

For the HAL issue is raised internally under ticket number 226146.

I keep you update when the issue is fixed.

Internal ticket number: 226146 (This is an internal tracking number and is not accessible or usable by customers).

 

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.