STM32 MCUs Products

Hi, SPI CR2 is missing from RM (RM0383 Rev 3) table in 20.5.10 SPI register map (page 610). Please update.   Best,Alessandro

Trying to get MD5 hash acceleration working on the Nucleo-H563Zi. I can get SHA1 hash engine to work via bootstrapping a project via CubeMX, but for some reason MD5 is not a selectable option for the hashing algorithm in CubeMX.  All other algorithms can be configured and work, but MD5 is not an option. The Datasheet for the STM32H562/3 says that the Crypto engine offers a MD5 hash, but I can't seem to configure it via CubeMX or by updating the generated code in hash.c to select the MD5 algorithm within MX_Hash_Init(). Is MD5 not supported on the H5?  There are no MD5 examples in the github example repo despite the datasheet claiming the crypto/hash accelerator supports MD5.

Hello, I have 2 NUCLEO-H563ZI boards connected to each other as required, one running the "I3C_Target_Private_Command_IT" example and the other running the "I3C_Controller_Private_Command_IT", i also have a logic analyzer connected to monitor the I3C communications, however the setup is not working as expected, the "target"  ACKs the initial broadcast from the "controller", but NACKs the subsequent broadcast after the "ENTDAA" CCC Any thoughts on what could be wrong here ? I tried debugging but the "target" board simply does not seem to be observing any interrupts/events during this whole "ENTDAA" CCC transmission

I've got some code running on the C4 in an STM32H747IGT6, it's just waiting for the ADC to have data and then reading it: while (!LL_ADC_IsActiveFlag_EOC(ADC1)) {} __disable_irq(); start_timer = TIM5->CNT; LL_ADC_ClearFlag_EOC(ADC1); adc_data = LL_ADC_REG_ReadConversionData32(ADC1); data = ((float)adc_data) / 65536.0f; // Normalize from 0..0xFFFF (-4 to 4V) to 0..1 end_timer = TIM5->CNT; uint32_t icsr = SCB->ICSR; __enable_irq();With IRQs disabled (as shown here), TIM5->CNT shows the code takes 6-8 ticks but if I comment out the calls to __disable_irq() and __enable_irq(), the code takes as many as 146 ticks and I'm trying to figure out why.  TIM5 has no interrupts enabled and is running at full speed (240 MHz) so ticking once every 4.1666 ns.If I look at the value of SCB->ICSR it's almost always 0x400000 which means ISRPENDING but VECTPENDING is zero.In

Moved from MPUs section - STM32L100 is an MCU, not an MPUI compare this my layout board (with outer st-linkv2 connected), and stm32l100c disco.stm32l100c disco does not have such a question. It will show "Error 57: Illegal Address(0x8000000)".And I disable download to flash, this error is disappeared.However, the program runs in 0x1ffffxxxx,not flash (0x8000000). It won't run my codes (no flash could be found?). I could not run my codes after download, either.But I am totally sure these codes could be executed in stm32l100c disco.And help?

Hello,I plan to use STM32G031Jx in a SO8N package and use embedded bootloader over UART.According AN2606, both USART1 and 2 can be usedBut PA3 is not available on SO8N, so remains only USART1.But USART1 is used by bootloader on PA9,10 which are not directly available on SO8N packages.These pins become available aft

I've been on an adventure trying to get my first CubeMX/STM32 project off the ground.  Here's as much context as I can give for my debugging process, and hopefully someone can spot what I'm missing. Dev Board: Nucleo-STM32H563ZIT-144 (Arm M33 Core)IDE: VSCode running STM32 V3 (Pre-Release) Toolchain (not using Clang -> using VSCode C/C++ Language Server for Intellisense) on Windows 11Build Tooling: CMake and GCC with code generated from CubeMX using FW/HAL v1.5.0Middlewares Used: ThreadX, NetXDuo, USBX Initial Debugging:First off, the rest of the code base has been working fine, the general ThreadX Application, Netx stack/App, and any additional code I have added hasn't generated unaligned access faults.  I have not been using the MPU, and have explicitly disabled it in the entrypoint using

Hello,I use a STM32F103 MCU and I use the RBIT instruction (as an CMSIS inline functinon). The instruction works properly and I can see the rbit instruction in the disassembly window (for this project I have to use an old TrueSTUDIO IDE).According to the ARM documentation this MCU could not execute the RBIT instruction because it is a Cortex-M3 r1p1 core (CPUID: 0x411fc231) which does not have this instruction. In spite of this the instruction seemly works and the "PM0056 Programming manual" (STM32F10xxx/20xxx/21xxx/L1xxxx) mentions too the instruction without making any difference about the revisions.Can someone help clear up this confusion?  

Hello, I have a problem with SysTick interrupt on STM32L072KZUX.I am using the latest version of STM32CubeIDE + the latest package for my MCU - FW_L0 1.12.3. An absolutely clean project, which was created in IDE and flashed into the device using ST-Link, starts up fine after flashing, but when the SysTick count reaches overflow and an interrupt should be called, for some reason the program goes to the wrong address (PC = 0x1ff00dd0), of course the interrupt handler itself is declared and there is a pointer to the function in the assembler file. Moreover, it does not matter which framework to use: LL or HAL. I checked the vector table both in the firmware image and in the microcontroller memory, all addresses are correct. Moreover, it does not matter how to use it. We checked it on 2 chips from the same batch, a similar program flashed into NUCLEO-L073RZ works correctly.

I have a question regarding internal PLLs.I would like to know the jitter of the PLL in the STM32H743XGH6.I could not find a PLL Characteristics table that would have the answer I want to know. I have seen posts about jitter in various other PLLs.However, I cannot decide how much to trust that information because of the different models.Perhaps it is very unlikely that these jitter values will adversely affect the system, but I would like to have some data to base my decision on. Does anyone know of any data on this?

Hi, i have a project here using an STM32U575RIT6Q with an external device i have connected throught the SPI interface.The microcontroller is at 160MHz using HSE with PLL. The SPI interface is at 40MHz with SPI mode 0, nss software and 8 bits per word.The problem surges when i call the function HAL_SPI_Receive. The reception of a long frame breaks up after some received bytes and then timeouts. Due to this timeout i cannot be able to receive the whole frame.I have made some test on the NUCLEO-U575ZI-Q using the 3 SPI peripherals to check if my SPI interface has any limitation. The result is the same.Here is the configuration for the SPI interfaces:/** * @brief SPI1 Initialization Function * @PAram None * @retval None */ static void MX_SPI1_Init(void) { /* USER CODE BEGIN SPI1_Init 0

Hello,When I read though AN5200 (Getting started with STM32H7 Series SDMMC host controller), I am not sure I fully understand the statement about UHS-I mode support in Table 2. (SDMMC1 and SDMMC2 main features) as in below screenshot, The table states that SD

Dear ST expert,   We want to upgrade from STM32G4 to STM32H7 dual core.       - Can you please suggest how to use CORDIC in STM32H745 series? If not then what is the best way to calculate sine and cosine of float values?         - Please suggest any alternate part no which has CORDIC and dual core combination     - Is there any other consideration needed to upgrade? We want to upgrade to dual core due to high throughput FDCAN link where one of the core, preferably M7, would be used entirely to handle FDCAN.         - Do you have any library or example codes for high throughput FDCAN link?   Regards, Jitendra Edited by ST Moderator to add the right labels

I started a new STM32G0B1 project based on the example project, ADC_MultiChannelSingleConversion, and added FreeRTOS. The default task makes the same HAL_ADCEx_Calibration_Start and HAL_ADC_Start_DMA ffunctino calls as the example, starts a periodic timer to fire every 10 ms and then goes into an infinite loop where all it does it repeatedly call  osDelay(1000).Every time the timer I started fires, it calls a function that increments a counter, toggles the green, LED,makes the same HAL_ADC_Start call the example does, delays, calls HAL_Delay(1), and then checks ubDmaTransferStatus, also the same way the example does I also print out the loop counter and the computed values from the example, plus a few more for seven altogether, and then clear ubDmaTransferStatus.But if ubDmaTransferStatus is not set, I print out a line of dashes.I eliminated the blue button entirely from the project

void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) { extern FDCAN_HandleTypeDef hfdcan1; if(hfdcan == &hfdcan1) { // printf("tx cplt = %d\n",BufferIndexes); can_tx_cplt = 1; } } void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) { // 错误处理 //printf("FDCAN Error Callback: ErrorCode=%lu\n", (unsigned long)(hfdcan->ErrorCode)); uint32_t error; error = HAL_FDCAN_GetError(hfdcan); if(error == 4) { can_init(); } printf("FDCAN Error = %d\n",error); } void can_send_msg(uint32_t id, uint8_t *data) { can_send_msg_len(id,data,3); } #if 1 void can_send_msg_len(uint32_t id, uint8_t *data,uint8_t len) { FDCAN_TxHeaderTypeDef FDCAN_Tx; static uint32_t can_tx_time_out_count = 0; extern FDCAN_HandleTypeDef hfdcan1; uint8_t retry_count = 0; bool flag = 0; FDCAN_Tx.TxFrameType = FDCAN_DATA_FRAME; FDCAN_Tx.TxEventFifoControl = FDCAN_NO_TX_EVENTS; FDCAN_Tx.MessageMarker = 0x00;

hii, i am using stm32 nucleo g0-b1re i am trying to receive data in interrupt mode, but cant figure out what is wrong, i am new to stm32 i2c protocol.i have used master as nucleo-h743zi2 and transmitting data, but it is not showing anything on minicom. 

Would STM32G4 performance gets effected if runs at lower voltage (1.8V)? Can the core clock run at max 170MHZ or it will run lower speed?

I am trying to configure the LPUART on my board, but appear to be getting nowhere. I've already configured the PLL to run at 110 MHz, and I changed the appropriate registers (`SW`) to use PLL as the system clock. I've tried flashing the board with Zephyr OS just to make sure that it works, and it indeed works. When I use GDB to inspect the relevant registers (the ones changed by my code below) they appear to all have the values that I expect. I can't for the life of me figure out what is going on. Using a logic analyzer, I see 0 activity on the TX pin, which is in a constant state of high. Here is my code for configuring my LPUART (I am using CMSIS). I want a baud rate of 115200, and my board is configured to run at 110 MHz.```#include <stdint.h> #include "stm32l5xx.h" void enable_lpuart1(void) { volatile uint32_t dummy; RCC->CCIPR1 &= ~(3 << RCC_CC

I am using the NUCLEO-L433RC-P development board and in the process of designing my own PCB.I would like to be able to update firmware via USB, but need to make sure my PCB design allows for this.Currently I have VDDUSB connected to 3.3V, but thinking this is now incorrect.The VDDUSB pin is not rated to 5V, so I can't connect the 5V from the USB-C connector to the VDDUSB pin.Presumably the VDDUSB is used to indicate to the MCU that the USB cable is connected ?  Is VDDUSB used as a signal or for power ?Should I just use a linear regulator to convert the USB 5V to 3.3V for the VDDUSB pin ?Also, the BOOT0 pin has to be pulled high to put the STM32 into bootloader mode.Can BOOT0 be connected to a pin on the USB-C connector ?Otherwise I would need an external connector to pull up the BOOT0 pin which does not seem user friendly. 

Hey All,I hope you can help me. I'm trying to bring up my new board, which contains a STM32N657IO. Attached are the schematics. You can assume the 5V supply is working(it is after a few bodge wires). My problem is as follows. I'm trying to connect to the STM32N6 over SWD using a JLink. It seems the SWD communication with the Debug port is successful, but the communication with the core fails. I get the following output when trying to connect to the MCU:Device "STM32N657I0" selected. Connecting to target via SWD ConfigTargetSettings() start ---Setting ETM Base Address--- ---Setting TF Base Addres

Hello Friends,I am Using STM32F303 MCU for my FULL Speed USB  communication board. Used interrupt transfer.Board is going to use in Noisy Industrial environment.So , Planned to use Shielded USB cable with EMI Chokes ( Both Side ).Cable Length is 1.8 Mtr.I plan  to use ESD / EMI ICs on the board before the MCU like ....USBUF01W6  "OR"  USBLC6-2SC6.Any Suggestion Which would be better out of two ? Regards,Bsuthar

Hi,I am trying to use the STM32H5 CRC unit via HAL to calculate a CRC32 (ISO-HDLC) over multiple chunks.This works correctly via:hcrc.Instance = CRC; hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE; hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_ENABLE; hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; if (HAL_CRC_Init(&hcrc) != HAL_OK) { Error_Handler(); } // calculate CRC32 over two identical chunks, HCRC keeps state! temp = HAL_CRC_Calculate(&hcrc, (uint32_t *)data, strlen(data)); // 0x444a273c crc = ~temp; // 0xbbb5d8c3 OK temp = HAL_CRC_Accumulate(&hcrc, (uint32_t *)data, strlen(data)); // 0x405e36b1 crc = ~temp; // 0xbfa1c94e OKNow I need to do something similiar as in

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Versi

I came across a discrepancy between two ST documents regarding the behavior of an IWDG reset on STM32H5 devices, and I’d like clarification on what exactly is reset when an IWDG event occurs.Document 1: UM3150 Rev 2 – STM32H5 Safety Manual, Table 9 (CPU_SM_6)States that the IWDG reset may result in an "incomplete" local safe state — it only resets the CPU and does not guarantee that application software can bring the system to a final safe state. This implies that I/O and peripherals may not be reset. Document 2: RM0481 Rev 2 – STM32

Hi all.I have a small problem understanding the timer 16 of the STM32G030K6T6 microcontroller. According to the data sheet, it should use the TIMPCLK clock, which corresponds to the PCLK clock.My system clock is supplied by the HSI (SYSCLK = 16 MHz). I have set my AHB prescaler to 4 and the APB prescaler to 1, so HCLK = PCLK = 4 MHz. Since my APB prescaler is equal to 1, the timer clock should be TIMPCLK = PCLK = 4 MHz.I then implemented a delay function with timer 16. So that the counter runs up in 1 us steps, I have to set the prescaler of the timer to 15 instead of 3. This means that the timer 16 still has a 16 MHz signal as an input signal.Now my question is: Have I misunderstood something here, is the data sheet wrong or is my code not correct? I have attached the