About CRCSIZE setting in STM32H7 SPI peripheral

[Gpeti]

I am confused about the setting of the SPI CRC functionality: it is not clear what CRCSIZE is doing and how to set it. I understand that to get a N bits CRC you have to choose a N+1 bits polynom, but why is the length of the CRC not deduced from the polynom size ? Why is there an additional field CRCSIZE ?

In my project I keep the standard 0x107 polynom since I want a 8 bits CRC. Should I set CRCSIZE to 00111 (8 bits) ?

[waclawek.jan]

CRC algorithms are of several size, it's the length of the shift register used in HW implementation of CRC.

If you want use 8-bit CRC, set CRCSIZE to 8-bit.

JW

[Gpeti]

But the size of the CRC is not exactly specified by the polynom ? I will set CRCSIZE, I just want to understand.

[waclawek.jan]

Yes and no. There's no unique definition of what exactly the polynom means - particularly, whether the MSB (here 0x100) which would then implicitly determine the poly size) should or should not be included.

But even if that MSB would be required to imply the CRC size, it's relatively complex in hardware to detect which bit is set; it's much easier for the hardware to have a register where the size is "told to it" explicitly.

Moreover, for 32-bit CRC, with MSB set, the poly a 33-bit number, which would be impractical to implement in a 32-bit mcu.

JW