Again, trouble with SDMMC2 on STM32H755 in 4 bit mode -> CRC fail

[Curtis B.]

Hello everybody,

after a long fight I got the SDMMC2 interface running in 1 bit mode on the STM32H755. I thought running it in 4 bit mode in the next step should be no big deal anymore; what a naive assumption...

The SDMMC is running with FATFS and FREERtos on the M7 core. The buffers for FATFS are located in RAM3. RAM3 is protected by the MPU so that DMA can work despite enabled cache.

In 1 bit mode everything works fine. I can mount the drive and I can write data. However, switching to 4 bit mode, mouting of the drive fails. I looked deeper into the code with the debugger and observed following behaviour:

The card init works fines and exits with no error. FATFS then reads the first sector (adress 0, 512 bytes) by means of DMA. Works fine. RxCmplt interrupt is called and the RTOS event releases the read function which returns no error. Data can be found in the read buffer.

Then, FATFS calls another DMA read operation. It tries to read another sector of 512 bytes at the address 8192. This is the first sector of the second cluster. This time the ISR returns HAL_SD_ERROR_DATA_CRC_FAIL. The RTOS event is not set and times out. The read function returns an error. But there is data in the receive buffer.

I have no idea, why the first read operation succeeds and the second fails. Has anyone encountert a similar problem? I hade already the 4 bit mode running on the STM32H743; but in that project it was on SDMMC1 and not SDMMC2...

Regards,

Daniel

[Imen.D]

Hello @Curtis B.​ ,

Have a look at this AN5200 "Getting started with STM32H7 Series SDMMC host controller", which contains typical examples and it may help you on the SDMMC configuration.

I will try to contact expert internally to get help.

Imen

[Curtis B.]

Hi Imen,

I have already read this application note, an I read it once again, but it does not provide any information regarding my problem. As I already mentioned: I had the SDMMC interface running on another H7 processsor. I know in principle how to set it up and how it "should" work. I got stuck on some weired behaviour I did not expected and I think I can rule out the standard don'ts like no pull ups, wrong clock prescaler, too long cables, DMA cache interference etc...

Regards,

Daniel

[TOlli]

Hi,

I remember having similar issues, but with a different stack (FreeRTOS + SafeFAT (HCC Embedded product) and with just plain operations.

My memory is a little hazy on what I did to correct the issue, but I mostly ended up playing with the SDMMC1 clock signal and the clock mux (for whatever reason, I could not get one or the other working) to get it working. Have you tried lowering your read/write speed by lowering the clock signal?

Best regards,

Tero

[Curtis B.]

Hi TOlli,

I measured the frequency on the CLK Pin, the frequency was set correctly. I also tried it with a lower clock speed. But that didn't help.

Regards,

Daniel