Enabling SFU_MPU_PROTECT_ENABLE causes a problem
In my project the microcontroller is STM32F756VGT6, I changed the example "2_Images_OSC" of STM32f769I-Discovery to be compatible with this microcontroller.
Right now everything seems O.K and I can upgrade the application with SBSFU. But when I uncomment the definition of SFU_MPU_PROTECT_ENABLE I get to a problem and here is the message I get from terminal:
======================================================================
= (C) COPYRIGHT 2017 STMicroelectronics =
= =
= Secure Boot and Secure Firmware Update =
======================================================================
= [SBOOT] SECURE ENGINE INITIALIZATION SUCCESSFUL
= [SBOOT] STATE: CHECK STATUS ON RESET
INFO: A Reboot has been triggered by a Software reset!
Memory fault
========= End of Execution ==========Here is the MPU config:
#define SFU_PROTECT_MPU_MAX_NB_SUBREG (8U)
/**
* @brief Region 0 - Enable the read/write operations for the full peripheral area in unprivileged
* mode.
* Execution capability disabled
*/
#define SFU_PROTECT_MPU_PERIPH_1_RGNV MPU_REGION_NUMBER0
#define SFU_PROTECT_MPU_PERIPH_1_START 0x00000000U
#define SFU_PROTECT_MPU_PERIPH_1_SIZE MPU_REGION_SIZE_4GB
#define SFU_PROTECT_MPU_PERIPH_1_SREG 0x83U /*!< 4GB / 8 * 5 ==> only peripheral area allowed */
#define SFU_PROTECT_MPU_PERIPH_1_PERM MPU_REGION_FULL_ACCESS
#define SFU_PROTECT_MPU_PERIPH_1_EXECV MPU_INSTRUCTION_ACCESS_DISABLE
#define SFU_PROTECT_MPU_PERIPH_1_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_PERIPH_1_B MPU_ACCESS_BUFFERABLE
#define SFU_PROTECT_MPU_PERIPH_1_C MPU_ACCESS_NOT_CACHEABLE
/**
* @brief Region 1 - Enable the read/write operations for RCC peripheral area in privileged mode.
* Execution capability disabled
* Inner region inside the Region 0
*/
#define SFU_PROTECT_MPU_PERIPH_2_RGNV MPU_REGION_NUMBER1
#define SFU_PROTECT_MPU_PERIPH_2_START RCC_BASE
#define SFU_PROTECT_MPU_PERIPH_2_SIZE MPU_REGION_SIZE_1KB
#define SFU_PROTECT_MPU_PERIPH_2_SREG 0x00U /*!< All subregions activated */
#define SFU_PROTECT_MPU_PERIPH_2_PERM MPU_REGION_PRIV_RW
#define SFU_PROTECT_MPU_PERIPH_2_EXECV MPU_INSTRUCTION_ACCESS_DISABLE
#define SFU_PROTECT_MPU_PERIPH_2_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_PERIPH_2_B MPU_ACCESS_BUFFERABLE
#define SFU_PROTECT_MPU_PERIPH_2_C MPU_ACCESS_NOT_CACHEABLE
/**
* @brief Region 2 - Enable the read/write operations for full flash area in unprivileged mode.
* Execution capability disabled
*/
#define SFU_PROTECT_MPU_FLASHACC_RGNV MPU_REGION_NUMBER2
#define SFU_PROTECT_MPU_FLASHACC_START FLASH_BASE /*!< Flash memory area */
#define SFU_PROTECT_MPU_FLASHACC_SIZE MPU_REGION_SIZE_1MB
#define SFU_PROTECT_MPU_FLASHACC_SREG 0x00U /*!< All subregions activated */
#define SFU_PROTECT_MPU_FLASHACC_PERM MPU_REGION_FULL_ACCESS
#define SFU_PROTECT_MPU_FLASHACC_EXECV MPU_INSTRUCTION_ACCESS_DISABLE
#define SFU_PROTECT_MPU_FLASHACC_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_FLASHACC_B MPU_ACCESS_NOT_BUFFERABLE
#define SFU_PROTECT_MPU_FLASHACC_C MPU_ACCESS_CACHEABLE
/**
* @brief Region 3 - Enable the execution for SB/SFU Full area (SBSFU + SE + Keys) in unprivileged mode.
* Read only capability configured
* Inner region inside the Region 2
*/
#define SFU_PROTECT_MPU_FLASHEXE_RGNV MPU_REGION_NUMBER3
#define SFU_PROTECT_MPU_FLASHEXE_START FLASH_BASE /*!< Flash memory area */
#define SFU_PROTECT_MPU_FLASHEXE_SIZE MPU_REGION_SIZE_128KB
#define SFU_PROTECT_MPU_FLASHEXE_SREG 0x00U /*!< All subregions activated */
#define SFU_PROTECT_MPU_FLASHEXE_PERM MPU_REGION_PRIV_RO_URO
#define SFU_PROTECT_MPU_FLASHEXE_EXECV MPU_INSTRUCTION_ACCESS_ENABLE
#define SFU_PROTECT_MPU_FLASHEXE_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_FLASHEXE_B MPU_ACCESS_NOT_BUFFERABLE
#define SFU_PROTECT_MPU_FLASHEXE_C MPU_ACCESS_CACHEABLE
/**
* @brief Region 4 - Enable the read/write operation in privileged mode for Header of active slots
* Execution capability disabled
* Inner region inside the Region 2
*/
#define SFU_PROTECT_MPU_HEADER_RGNV MPU_REGION_NUMBER4
#define SFU_PROTECT_MPU_HEADER_START SLOT_ACTIVE_1_HEADER
#define SFU_PROTECT_MPU_HEADER_SREG 0x00U /*!< All subregions activated */
#define SFU_PROTECT_MPU_HEADER_SIZE MPU_REGION_SIZE_1KB
#define SFU_PROTECT_MPU_HEADER_PERM MPU_REGION_PRIV_RW
#define SFU_PROTECT_MPU_HEADER_EXECV MPU_INSTRUCTION_ACCESS_DISABLE
#define SFU_PROTECT_MPU_HEADER_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_HEADER_B MPU_ACCESS_NOT_BUFFERABLE
#define SFU_PROTECT_MPU_HEADER_C MPU_ACCESS_CACHEABLE
/**
* @brief Region 5 - Enable the read/write operation in unprivileged mode for RAM area.
* Execution capability disabled
*/
#define SFU_PROTECT_MPU_SRAMACC_RGNV MPU_REGION_NUMBER5
#define SFU_PROTECT_MPU_SRAMACC_START RAMDTCM_BASE /*!< RAM memory area */
#define SFU_PROTECT_MPU_SRAMACC_SIZE MPU_REGION_SIZE_512KB
#define SFU_PROTECT_MPU_SRAMACC_SREG 0xE0U /*!< 512 Kbytes / 8 * 5 ==> 64K + 240K Kbytes */
#define SFU_PROTECT_MPU_SRAMACC_PERM MPU_REGION_FULL_ACCESS
#define SFU_PROTECT_MPU_SRAMACC_EXECV MPU_INSTRUCTION_ACCESS_DISABLE
#define SFU_PROTECT_MPU_SRAMACC_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_SRAMACC_B MPU_ACCESS_NOT_BUFFERABLE
#define SFU_PROTECT_MPU_SRAMACC_C MPU_ACCESS_CACHEABLE
/**
* @brief Region 6 - Enable the read/write operation in privileged mode for Secure Engine RAM area.
* Execution capability disabled
* Inner region inside the Region 5
* Address must be aligned on 4KB as size is 4KB
*/
#define SFU_PROTECT_MPU_SRAM_SE_RGNV MPU_REGION_NUMBER6
#define SFU_PROTECT_MPU_SRAM_SE_START SFU_SENG_RAM_ADDR_START /*!< SE RAM memory area */
#define SFU_PROTECT_MPU_SRAM_SE_SIZE MPU_REGION_SIZE_16KB
#define SFU_PROTECT_MPU_SRAM_SE_SREG 0xC0U /*!< 16 Kbytes / 8 * 6 ==> 12 Kbytes */
#define SFU_PROTECT_MPU_SRAM_SE_PERM MPU_REGION_PRIV_RW
#define SFU_PROTECT_MPU_SRAM_SE_EXECV MPU_INSTRUCTION_ACCESS_DISABLE
#define SFU_PROTECT_MPU_SRAM_SE_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_SRAM_SE_B MPU_ACCESS_NOT_BUFFERABLE
#define SFU_PROTECT_MPU_SRAM_SE_C MPU_ACCESS_CACHEABLE
/**
* @brief Region 7 - Enable the execution for Secure Engine flash area in privileged mode.
* Read only capability configured
* Inner region inside the Region 3
*/
#define SFU_PROTECT_MPU_EXEC_SE_RGNV MPU_REGION_NUMBER7
#define SFU_PROTECT_MPU_EXEC_SE_START FLASH_BASE /*!< Flash memory area */
#define SFU_PROTECT_MPU_EXEC_SE_SIZE MPU_REGION_SIZE_64KB
#define SFU_PROTECT_MPU_EXEC_SE_SREG 0x00U /*!< All subregions activated */
#define SFU_PROTECT_MPU_EXEC_SE_PERM MPU_REGION_PRIV_RO
#define SFU_PROTECT_MPU_EXEC_SE_EXECV MPU_INSTRUCTION_ACCESS_ENABLE
#define SFU_PROTECT_MPU_EXEC_SE_TEXV MPU_TEX_LEVEL0
#define SFU_PROTECT_MPU_EXEC_SE_B MPU_ACCESS_NOT_BUFFERABLE
#define SFU_PROTECT_MPU_EXEC_SE_C MPU_ACCESS_CACHEABLE
/**
* MPU configuration for UserApp execution
* =======================================
* Reconfiguration of existing regions (useless during UserApp execution)
* MPU constraint = Region base address should be aligned on Region size
*/
/**
* @brief Region 3 - Enable the execution for active slots in unprivileged mode.
* Read only capability configured
* Inner region inside the Region 2
*/
#define APP_PROTECT_MPU_FLASHEXE_RGNV MPU_REGION_NUMBER3
#define APP_PROTECT_MPU_FLASHEXE_START FLASH_BASE
#define APP_PROTECT_MPU_FLASHEXE_SIZE MPU_REGION_SIZE_1MB
#define APP_PROTECT_MPU_FLASHEXE_SREG 0xCCU /*!< subregion 0 (activated): SBSFU
subregion 1 (de-activated) : Swap
subregions 2,3,4 (activated) : active slot(s) */
#define APP_PROTECT_MPU_FLASHEXE_PERM MPU_REGION_PRIV_RO_URO
#define APP_PROTECT_MPU_FLASHEXE_EXECV MPU_INSTRUCTION_ACCESS_ENABLE
#define APP_PROTECT_MPU_FLASHEXE_TEXV MPU_TEX_LEVEL0
#define APP_PROTECT_MPU_FLASHEXE_B MPU_ACCESS_NOT_BUFFERABLE
#define APP_PROTECT_MPU_FLASHEXE_C MPU_ACCESS_CACHEABLEWhat is wrong with this MPU config?
