What is the MIPS figure for X-CUBE-CRYPTOLIB HMAC SHA-256 Implementation for STM32F429 (Cortex M4)?

[Torben1]

Hi,

I'm looking into introducing HMAC SHA-256 on my STM32F429 based project as part of a requirements change.

As a first go/no go, I'll need to know what is the worst case required MIPS figure and memory foot print (SRAM/FLASH) for running the algorithm on a data entry of up to 255 bytes stored in internal SRAM?

Thanks,

Torben

[Tesla DeLorean]

Would suggest you mock up the hashing and evaluate cycles counts via DWT CYCCNT