LoRaWAN End Node Dual Core - Can't Update Flash Map in Linker File for CM0+ Core

[dbdev]

MCU: STM32WL55JC1

FW Version: STM32Cube_FW_WL_V1.3.1

Reference: LoRaWAN_End_Node_DualCore

Compiler/Debugger: STM32CubeIDE

Issue:

I am trying to expand the flash memory region for the CM4 application by reducing the flash memory region of the CM0+ application. When trying to modify `STM32CubeIDE/CM0PLUS/STM32WL55JCIX_FLASH.ld`: 

From:

FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 120K

To:

FLASH (rx) : ORIGIN = 0x0802A000, LENGTH = 80K

The CM0+ core will never synchronize and the applications on both cores are unable to proceed. The CM4 core boots fine, but hangs waiting for the CM0+ core. If I only reduce the LENGTH of the CM0+ core it proceeds without issue.

I have also tried to modify `Common/System/system_stm32wlxx.c` by defining USER_VECT_TAB_ADDRESS and adjusting the VECT_TAB_OFFSET with no success.

What is the correct way to modify the flash allocations?

[STTwo-32]

Hello @dbdev 

Could you please give more details about the changes you maid to have this issue.

Best Regards.

STTwo-32

[bmckenney]

CPU2 boots according to the setting of SBRV (along with C2OPT) in FLASH->SRRVR [Ref RM0453 rev 3: Sec 2.3 and 4.10.20]. Out of the box, SBRV=0x8000 (and C2OPT=1), so it will boot from 0x08020000, which won't have the reset vector after you change the ORIGIN.

If you're not running in Secure mode (and you haven't changed C2BOOT_LOCK=0) I expect you can just write a different value into SRRVR:SBRV and then boot CPU2. [I haven't tried it.]