STM32WL RF Layout – Routing Signals on 3rd Layer Near RF Section & Stack-up Changes

[Eranga]

Hi everyone,

I’m working on a 4-layer PCB design using the STM32WL (based on the Nucleo WL55JC reference design).

For the RF section, I followed the same layout approach as the Nucleo board, including the layer stack-up and RF trace widths.

The only difference in my design is that I have some GPIO signals routed close to the RF section. These signals are routed on the 3rd layer, while I am still maintaining solid ground planes on the 2nd and 3rd layers underneath the RF section.

I would like to clarify:

• Is it acceptable to route non-RF signals on the 3rd layer near the RF section if solid ground planes are maintained?
• Are there any risks (e.g., noise coupling or RF performance degradation) with this approach?

Additionally, if I modify the layer stack-up:

• What parameters need to be adjusted (e.g., RF trace width, impedance matching, ground reference)?
• Are there any recommended guidelines for maintaining RF performance when changing the stack-up?

Any guidance or best practices would be greatly appreciated.

Thanks in advance!

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