Solved
STM32WL5 Design review
- January 28, 2025
- 1 reply
- 811 views
Dear STM32 Community,
I am working on a PCB design for the STM32WL5 and would like to seek confirmation regarding my design approach. Specifically, in the top layer, I have an RF signal track, and in the second layer, there is a GND plane. However, I have cut the GND plane directly below the RF signal track.
Could you please confirm if this design approach adheres to best practices, or if there are any potential issues with this configuration? I would appreciate any guidance or suggestions based on your experience with STM32WL5 designs.
Looking forward to your feedback.
Thank you in advance!
