How to transfer data from the SRAM to the DDR in a kernel module?

[MElha.1]

Hello,

I am working on a project that acquires ADC readings and saves them into a buffer in the M4 side of STM32mp157 chip on DK2 board, now I need to build a kernel module that copies the saved buffer from the SRAM to DDR on the A7 side when a certain interrupt is triggered.

As I am a beginner in embedded linux world I am wondering about the way to do this, I tried memcpy() at first but errors arise when inserting the module (Can't page virtual address error), I also tried converting the SRAM address from physical to virtual before memcpy() but that didn't work as well.

Is there a direct way to copy data between the memories like memcpy() or do I need to use DMA from the kernel module to copy the data, if the DMA is the way, sharing an example would be great.

Thanks

[Olivier GALLIEN]

Hi @MElha.1​ 

ST deliver a complete documentation and demo for this use case :

https://wiki.st.com/stm32mpu/wiki/How_to_exchange_large_data_buffers_with_the_coprocessor_-_principle

https://wiki.st.com/stm32mpu/wiki/How_to_exchange_large_data_buffers_with_the_coprocessor_-_example

Hope it help

Olivier

[MElha.1]

That seems to be very helpful, thank you very much Oliver.

The example is based on the distribution package which I didn't use before, so I am working on it and will give you a feedback if I have any further problems or questions.. thanks again.

M. Elhawy

[Olivier GALLIEN]

​Hi @MElha.1​ 

As a example we achieved 65MB/s on the provided "How to exchange large data buffers with coprocessor" exemple by removing compression on M4 side and backup in FS on Linux side.

Maximum b/w achievable is really dependant on use case and implementation. We cannot guarantee to exceed 100MB/s.

In order to identify potential bottleneck in your implementation we need to know better about your use case.

Could you share some details about implementation : DMA managment, RAM and DDR buffer size used etc ?

If you agree, sharing your complete application by private message could also be a very useful option.

BR,

Olivier

[MElha.1]

Hi Oliver,

Thank you very much for your fast reply. After reading your reply and knowing that 65MB/s is achievable, I optimized the DMA configuration and that made me reach about 60MB/s and I then discovered that the real bottle neck in the example and also in my use case is using the same DMA engine for both transfers from GPIO to SRAM and from SRAM to DDR; With the first stream (GPIO to SRAM) having higher priority it can greatly affect the transfer speed of the second lower priority stream from SRAM to DDR specially when increasing the sampling rate. Even a sampling rate of 15 MSample/s can't be achieved by this configuration and results in failure on the second DMA stream to DDR. One solution I made for this problem is configuring one DMA engine for the transfer from the GPIO to the SRAM and the other DMA engine for the transfer from the SRAM to DDR, with this configuration I reached transfer rates to DDR of higher than 120 MB/s without having problems also with a sampling rate from the GPIOs of 40 MSample/s.

BR,

Elhawy

[Olivier GALLIEN]

Hi @MElha.1​ 

Thanks for feedback.

Do you mean you allocate DMA1 to M4 context ?

Thx

Olivier