Is it possible to drive a three lane DSI display with two lanes?

[BSunw.1]

I was planning on using the STM32MP157A-DK2 to drive a three lane DSI display but the Microcontroller only supports two lanes..

[Tesla DeLorean]

A bit overly general, check the controller spec for the display in question, likely a configurable setting.

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Problem would be if it needs three to sustain bandwidth for display resolution, colour depth and frame rate​, and remain under the maximum clock ceiling.

[BSunw.1]

Here is a link to the driver manual, ILI9881C. It looks like it is configurable in hardware, "The ILI9881C supports DSI interfaces. The interface mode and the lane number of DSI interface can be selected by hardware pins IM[2:0], LANSEL and control register MIPI_LANE_SEL (Page4_R00h)." So I think I am out of luck as it would be very difficult to make any mods to the display ic.

The display data sheet can be found here: TM034XDZP02

[Tesla DeLorean]

The IC says it can be used in 2, 3 or 4 lane mode.

It has an internal frame buffer it is using to paint the display, the DSI is simply the deliver pipe.

You'll need to know the default configuration of IM pins to decode the table options.

>>So I think I am out of luck as it would be very difficult to make any mods to the display ic.

I guess you'd need to look at the current STM32MP side DSI display drivers, I suspect most need some configuration.

If you're ordering enough displays the vendor can usually change strapping options to meet actual customer requirements. Most of the STM32 family of parts only support 2 lanes.

[dorijan]

I have a similar question for someone that is more knowledgeable with DSI.

Controller is ILI9881D which I would assume is successor of the ILI9881C. (i did request a datasheet from manufacture but not received it jet), but looking at the ILI9881C datasheet it does require LANSEL HW pin and IM0-2 to be set correctly additionally to MIPI_LANE_SEL register .

Display is EDT ETML050015DHA

https://www.glynshop.com/erp/owweb/Daten/DSS/EDT/Products/Specifications/Active%20Displays/ETML050015DHA%20Ver.2-RoHS.pdf

Datasheet does mention max recommended refresh rate for 2-lane DSI but does not really specify how to set it.

MCU is STM32MP157C on a KaRo QSMP module.

[Tesla DeLorean]

The host defines the clocking/framing

In Linux this is usually expressed via line totals, and refresh rates, the pixel clocks and wire speeds then evolve from those.

The ceiling is 500 Mbps per lane, as I recall 250MHz, both edges.