MDIO communication with DP83867 not working under u-boot and Linux

[werwolv98]

Hi

I'm designing a custom PCB with a STM32MP157F and a DP83867 PHY connected over MDIO and RGMII. The problem is, the communication between the two is completely dead. No data or clock can be measured on either the MDIO or MDC line, MDIO is constant HIGH and MDC is constant LOW, even when explicitly reading/writing data using the mii or mdio u-boot subsystem.

The following code is my u-boot device tree configuration:

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy0>;
 
	mdio0 {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
 
		phy0: ethernet-phy@0 {
			reg = <0>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
			ti,min-output-impedance;
			ti,dp83867-rxctl-strap-quirk;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
 
		};
	};
};

Is it possible that I misconfigured the mdio interface or could there be a different error?

Thanks a lot and best regards

[PatrickF]

Hi,

Could you share more information ?

Any error/warning log messages ?

Did it fail under Linux as well ?

Which ecosystem version are you using ?

Some thoughts:

• Check your HW around PHY (supply, clocks, reset, etc...).
• Check you are using correct ETH1_MDC (PC1) and ETH1_MDIO (PA2) pins.

AN5031 could be helpful as well as https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_Crystal_on_PHY-2C_CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29_is_provided_by_a_Phy_Crystal-29

Regards.