STM32MP fast data exchange between M4 and A7

[Michael Schmid]

Dear all,

how can the Cortex-M4 MCU (bare metal or RTOS) exchange data fast with the A7-Linux system? Can the M4 access the DDR RAM of the Linux system, like the PRU on the Beaglebone can do? In the datasheet, there is a connection between the AHB bus and the AXI bus, maked as asynchronous, so it looks like there is a DMA channel for this.

I could not find an example code or project, showing a fast data exchange between the memories of M4 and A7. Does ST provide an example for this?

Thanks,

Michael

[Olivier GALLIEN]

Hi,

Cortex-M4 is not intended to access DDR content. Cortex-M4 has no cache and asynchronous path to AXI bus has not been optimized for that, so Cortex-M4 performance will be very largely impacted.

Furthermore, accessing small chunk of data to a DDR is never a good choice, as this will affect the DDRCTRL scheduling and so the performance of other AXI masters accessing the DDR SDRAM.

Although it is possible from HW point of view, in our Linux deliveries, Cortex-M4 access is forbidden inside TrustZone address space controller for DDR (TZC).

For data exchange between A7 and M4 please have a look to discussion on this post.

https://community.st.com/s/question/0D50X0000AnuE1XSQU/what-is-the-maximum-transmission-interprocessor-bandwidth-on-stm32mp

Hope it help

BR,

Olivier