Stm32mp157 ethernet with fixed PHY not working

[aunoor]

Hello.

I'm trying to connect MP1's eth to Marvell 88E6352. Switch connected to cpu via RGMII.

Because switch don't have output 125MHZ clock, eth configured to use internal clock, how described in this article: https://community.st.com/s/question/0D50X0000B8iBSB/stm32mp157-ethernet-problem

After all connections and configurations Linux can see Marvell's switch. But when I try to enable eth, it's not started and write this to console:

root@stm32mp1:~# ifconfig eth0 up
[ 107.460160] Generic PHY fixed-0:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=fixed-0:00, irq=POLL)
[ 108.476843] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[ 108.481623] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 108.490893] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed
ifconfig: SIOCSIFFLAGS: Device or resource busy

I can't solve this problem by myself.

[Christophe Guibout]

Hi @Community memberomissarov​ ,

Could you please share the following informations to progress on the analysis :

• What is the MMDV version ?
• Can you provide your device tree and kernel logs ?

Thanks,

BR,

Christophe

[aunoor]

Hi Christophe,

Thank you for answering.

As base for my firmware I use Yocto_Install1-1 (version: 1.1.0) from there:

https://www.st.com/content/st_com/en/products/embedded-software/mcu-mpu-embedded-software/stm32-embedded-software/stm32-mpu-openstlinux-distribution/stm32mp1distrib.html

dts files for u-boot and kernel in attach, also with dmesg and clk_summary dumps.

WBR, Dmitry

[PatrickF]

Hi,

for HW point of view, this kind of error is usually shown because the ETH GMAC IP does not receive rx and tx clock. looking at Reference Manual figure "Peripheral clock distribution for Ethernet" might help to see which settings are needed. This wiki article and AN5031 could also help.

[aunoor]

Hello, @PatrickF

My clk_summary contains next values:

 ref3 1 1 0 24000000 0 0 50000
 pll3 2 2 0 624999609 0 0 50000
 pll3_r 0 0 0 11160708 0 0 50000
 pll3_q 1 1 0 124999922 0 0 50000
 ethptp_k 0 0 0 124999922 0 0 50000
 ethck_k 1 1 0 124999922 0 0 50000
 ...
 ref1 2 2 0 24000000 0 0 50000
 pll2 2 2 0 533000000 0 0 50000
 pll2_r 1 1 0 533000000 0 0 50000
 pll2_q 0 0 0 533000000 0 0 50000
 gpu_k 0 0 0 533000000 0 0 50000
 pll2_p 1 1 0 266500000 0 0 50000
 ck_axi 8 9 0 266500000 0 0 50000
 ...
 ethstp 0 0 0 266500000 0 0 50000
		 ...
 ethmac 1 1 0 266500000 0 0 50000
 ethrx 1 1 0 266500000 0 0 50000
 ethtx 1 1 0 266500000 0 0 50000
 ...

As I can understand, ETH have rx and tx clocks. Or I'm wrong?

[PatrickF]

As I'm HW guy, I cannot rely/check if SW log is ok.

Apart 125MHz settings, to be sure, you could check directly low level registers setting (mostly SYSCFG and RCC) according to your expectations regarding "Peripheral clock distribution for Ethernet" clock paths.