STM32MP157AA3 LTDC

[NPal.2]

Hi all,

I am currently using VisionSoM board : STM32MP157AAB3 board.

I am trying to drive an LVDS display via a RGB to LVDS converter.

Here is the datasheet link for it.

The panel settings are as follows :

	panel {
	 u-boot,dm-pre-reloc;
	 status = "okay";
 display-timings {
 timing0: timing0 {
 clock-frequency = <72400000>;
 hactive = <1280>;
 vactive = <800>;
 hfront-porch = <22>;
 hback-porch = <150>;
 hsync-len = <160>;
 vback-porch = <32>;
 vfront-porch = <22>;
 vsync-len = <38>;
 hsync-active = <0>;
 vsync-active = <0>;
 de-active = <0>;
 pixelclk-active = <1>;
 };
 };
	};

I also modified the driver : panel-simple.c file in kernel/drivers/gpu/drm/panel and added support for this custom display there.

When i run qt demo for playing video on the RGB out i can see on oscilloscope that the clock signal frequency is not going beyond 66.6Mhz .

Earlier I was stuck at clock generation frequency of 33.3Mhz since my changes in device tree were getting ovewritten by the one's in kernel driver since i set the compatible field in device tree to some other display.

But now when i want to generate if for 72.4 Mhz , it is not going beyond 66.6Mhz ?

I am running OpenSTlinux dunfell 5.10 latest version.

[PatrickF]

Hi,

what is your PLL4 frequency (e.g. using "cat /sys/kernel/debug/clk/clk_summary | grep pll4") ?

In Starter Package, the PLL4 frequency is set to 594MHz which mean you can't output precisely 72.4MHz for LTDC pixel clock (pll4_q) with an integer divider (594/72.4 = 8.204...).

Linux will fallback to next possible integer divider (594/9 = 66MHz).

Maybe worth to try using 74.25MHz (594/8) for LTDC pixel clock (this frequency is the one used when we display using LTDC going to HDMI bridge).

See also https://wiki.st.com/stm32mpu/wiki/DRM_KMS_overview.

Regards.

[NPal.2]

@PatrickF​ : Thanks a lot for response this really helped.