USB-OTG traffic from/to the Cortex-M4 core (STM32MP1)

[APeña.1]

Hello,

I am trying to figure out how to drive the USB traffic (any of the available ports acting as device) from/to the M4 core. I can see that the SoC interconnection allows for the data to flow between the peripheral and the M4 core but I cannot find a way to achieve this form of operation.

The runtime operation of the USB-OTG peripheral is assigned to the A7 core but I assume there is a way to allow the endpoint data to be handled by the M4 core in some way (maybe some DMA-based scheme?). I would really appreciate if somebody can cast some light over this issue to get started evaluating this use case.

The target application requires real-time operation for the data being transmitted over USB and this feature being handled by the M4 core is quasi-mandatory. I do not see a clear way of achieving the real-time performance by transmitting all the data over the IPCC interface, even using indirect more, as this would require a very high frequency polling of this memory region by the A7 core.

Thank you very much in advance.

[APeña.1]

Update: I could see several references to the USB-OTG in the CM4 HAL but can still find no driver or support for the peripheral. Is there anything provided by STM I could be missing?