DDR Batch Simulation with STM32MP135 IBIS model

[MB.13]

Hi Team,

 

I am working on DDR3L batch simulation in Hyperlynx with STM32MP131 series processor. While assigning the appropriate ODT models, I am getting some errors with respect to IBIS model. So please help me in rectifying the issues

PFA error log as well

Also, currently I am using STM32MP135 series IBIS file for STM32MP131 I could not find the proper IBIS file. If any IBIS is there for STM32MP131 please do share that as well

 

Warm Regards,

Mythili B

[PatrickF]

Hi @MB.13 ,
I'm not expert in this, but did you have a look to AN4803 (High-speed SI simulations using IBIS and board-level simulations using HyperLynx® SI on STM32 MCUs and MPUs)?

Regards.

[MB.13]

Hi Patrick,

 

Thanks for your reply

Yes, I have looked into AN4803 for simulation reference but facing some issue in the IBIS model. Can you share the proper IBIS model for STM32MP131AAE3 part.

 

Warm Regards,

Mythili B

[PatrickF]

I guess that as MP131 is a subset of MP135 while using same DDR interface, same IBIS model could be used.

I think you are assigning wrong model to IOs. e.g. I see you are using MSD_D3RP3L_ODT60 for Address while AN4803 section "HyperLynx simulation with DDR3L" mention to use MSD_D3RP3L_48.
ODT is only for DQ/DQS/DM when simulated in input direction (i.e. read).

Regards.

[MB.13]

Hi,

For address I have assigned MSD_D3RP3L_48 model only, since address and data is sharing the same IBIS model selector in IBIS file it is throwing an error. So could you please share the IBIS file which has separate IBIS model selectors for data and address

 

Warm Regards,

Mythili B

[FredL]

Hi Mythili B,
Please apply the corrections attached in the txt files.
1- remove the comments for diff pin
2- add receiver thresholds for MSD_D3RP3L_48
3- change model type of MSD_D3RP3L_ODT60 in I/O
4-add receiver thresholds for MSD_D3RP3L_ODT60

You can keep MSD_D3RP3L_48 for address even an error is mentioned by Hyperlynx .

Rgs