Skip to main content
R
Roman Andronov
Associate
January 29, 2024
Solved

how to activate level 2 cache for stm32mp157 ?

  • January 29, 2024
  • 1 reply
  • 1044 views

..

This topic has been closed for replies.
Best answer by PatrickF

Hi @Roman Andronov 

The L2 is enabled together with L1 data cache.

See bit C in https://developer.arm.com/documentation/ddi0464/f/System-Control/Register-descriptions/System-Control-Register?lang=en

Obviously, need MMU correctly setup and SMP=1 (mandatory to have data cache) as well as I (for instruction cache).

Regards.

1 reply

PatrickF
PatrickFBest answer
Technical Moderator
January 30, 2024

Hi @Roman Andronov 

The L2 is enabled together with L1 data cache.

See bit C in https://developer.arm.com/documentation/ddi0464/f/System-Control/Register-descriptions/System-Control-Register?lang=en

Obviously, need MMU correctly setup and SMP=1 (mandatory to have data cache) as well as I (for instruction cache).

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.NEW ! Sidekick STM32 AI agent, see here
Terms & ConditionsAccessibility statement