If HSEM_CnIER registers of STM32MP2 have global access attribute?

[Da_Vinci]

Hi,

In STM32MP25x Reference manual(RM0457), the HSEM_(S)Cnxxx registers all have the description of global access attribute except HSEM_CnIER, 
as shown of HSEM_CnICR,

22.5.4 HSEM non-secure interrupt clear register (HSEM_CnICR)
Address offset: 0x104 + 0x010 * (n - 1), (n = 1 to 3)
Reset value: 0x0000 0000
Register global access: When CID filtering for processor[n] is enabled in
HSEM_CnCIDCFGR, this register can be accessed only by the processor CID. An illegal
CID access to this register generates a CID illegal access event. When CID filtering for
processor[n] is disabled this register can be accessed by any bus master.

the  HSEM_SCnIER also have the description of global access attribute, and the bits of HSEM_CnIER register also have CID filtering access attribute, and all bits maybe could be used by one CID , So if HSEM_CnIER also have  the  global access attribute？

 

[GatienC]

Hello,

I'm not sure I understood the question to its full extent but I'll try to respond.

HSEM_CnIER register CID filtering is either:

• HSEM_GpCIDCFGR.CFEN is unset -> CID filtering disabled, and access is only restricted by secure and privileged level defined in HSEM_SECCFGR and HSEM_PRIVCFGR
• HSEM_GpCIDCFGR.CFEN is set -> CID filtering enabled. The semaphore is accessible by the CID pointed by the white-listed group defined in HSEM_GpCIDCFGR.

Exemple, BIT(16) of HSEM_G1CIDCFGR is set => Proc1 CID defined in HSEM_C1CIDCFGR can access semaphores p = 0 Group HSEM3:0. If it was BIT(17), then it would be the CID of the proc2 defined in HSEM_C2CIDCFGR. It's a bitfield so  I guess multiple proc can be white-listed.

I hope this helps,

Gatien

 

[Da_Vinci]

Hi,Gatien,

    Yes, the attribute of the bit in HSEM_CnIER is clearly.

I mainly just want to confirm that , since the HSEM_SCnIER  register and HSEM_CnICR  register all have the attribute of "Register global access", does the HSEM_CnIER register also have this attribute?