Can't get F746ZG Nucleo ethernet to work with the LwIP example on CubeIDE.

[TOzca.1]

I have a Nucleo F746ZG board with 8742A Phy. I am just trying to ping the device. I compiled and ran the LwIP example. The device IP doesn't show when looked at from the terminal (arp -a). JP6 and JP7 are on and the board is on stock configuration. On board, LEDs indicate that the link is connected, ethernet port LEDs are also working. What might be the problem with this issue?

[Walid ZRELLI]

Hello @TOzca.1​ ,

Are you using DHCP or static IP configuration?

Thanks in advance.

BeST Regards,

Walid

[TOzca.1]

Walid,

Thank you for responding. I was using static IP configuration. I was able to track the issue down to the phy configuration. Turns out not all nucleo boards ship with the same phy and STM32CubeIDE doesnt have the right configuration for 8742A with the default settings. For anyone else having the same problem the correct configuration is given below.

PHY_Address = 0

PHY Special Control/Status register Offset - 0x1F

PHY Speed Mask - 0x0004

PHY Duplex Mask - 0x0010

PHY Interrupt Source Flag Register Offset - 0x001D

PHY Link Down Interrupt - 0x0010

Regards,

Tuna

[Walid ZRELLI]

Thanks for sharing the solution :smiling_face_with_smiling_eyes:

[Piranha]

For everyone... Here is a discussion about adding a support for any PHY chip:

https://community.st.com/s/question/0D53W00001BvNWbSAN/need-support-for-interfacing-dp83620-driver-with-smt32h753-in-rmii-mode

@Khouloud ZEMMELI​, my other (earlier) comment and this topic itself describes a very old CubeMX bug, which is still not fixed.

[MSG_ST]

Hi,

Issue confirmed.

The right generated code should be as follow :

If DP83848 PHY is selected :

• #define DP83848_PHY_ADDRESS 0x01U
• #define PHY_SR ((uint16_t)0x10U)
• #define PHY_SPEED_STATUS ((uint16_t)0x0002U)
• #define PHY_DUPLEX_STATUS ((uint16_t)0x0004U)

If LAN8742 PHY is selected :

• #define LAN8742A_PHY_ADDRESS 0x00U
• #define PHY_SR ((uint16_t)0x001FU)
• #define PHY_SPEED_STATUS ((uint16_t)0x0004U)
• #define PHY_DUPLEX_STATUS ((uint16_t)0x0010U)
• #define PHY_ISFR ((uint16_t)0x1D)
• #define PHY_ISFR_INT4 ((uint16_t)0x0010)

An Internal ticket ID 142215 is already created to solve this issue

(PS: This is an internal tracking number and is not accessible or usable by customers).

Sorry for the delayed answer.

Regards

Mahdy

[Pajdoom]

I couldn't find the settings for LAN8742 anywhere in the generated source codes. Is there a code generation guide for the NUCLEO-F767ZI for USB and LAN in CubeIDE 1.11.2 available somewhere?

[Piranha]

For the newer rewritten Ethernet drivers the PHY code has been moved into a separate driver modules. Just select the correct PHY part number and that's it.

But be aware of everything else:

https://community.st.com/s/question/0D50X0000BOtfhnSQB/how-to-make-ethernet-and-lwip-working-on-stm32

[Pajdoom]

In CubeIDE 1.11.2

1. File -> New -> STM32 Project

2. Target Selection -> Tab Board Selector -> Select "NUCLEO-F767ZI" and Next

3. Write Project Name and Location, and Next and Finish

4. Initialize all peripherals = yes

5. Now i have prject .ioc in CubeIDE

6. Change in .ioc

6.1 Tab Pinout -> Middleware -> LWIP -> Enabled, and 

6.1.1 Platform Settings -> Driver_PHY -> LAN8742 (Both combo)

6.2 Tab Pinout -> Middleware -> USB_DEVICE -> Select Virtual Port Com

6.3 Tab Clock -> No Change

6.4 Tab Project Manager -> Code Generator -> Generate peripheral initialization as a pair of ...

6.5 Tab Project Manager -> Advanced Settings -> GPIO Change to LL

7. Save -> Generate Code ? = YES

8. change main.c main loop to

 while (1)

 {

LL_GPIO_TogglePin(LD1_GPIO_Port, LD1_Pin);

LL_mDelay(250);

MX_LWIP_Process();

   /* USER CODE END WHILE */

   /* USER CODE BEGIN 3 */

 }

9. Compile -> No Errors

10. Flash to board

11. On My Router no info about IP for NECLEO, Green LED blinking

12. If I flash Piranha Demo NUCLEO-144.hex IP Succsec, and WEB on NUCLEO working ...