DFSDM filtre synchronization issue in CubeMX
Moved from STM32H7B0 DFSDM Synchronization: Abnormal Clock Output During Register Configuration to a new thread in STM32CubeMX forum.
Thank you for your detailed instructions!
I set a breakpoint as you suggested and found that the audio clock is indeed generated as you said, but its behavior is abnormal, and not modified by codes after.
Unfortunately, I cannot measure the waveform of the audio clock (DFSDM1 ACLK) directly, as it is not mapped to any IO output by default.

To debug this, I re-mapped the DFSDM1 clock output (DFSDM1_CKOUT) from PC2_C to PB0. Surprisingly, the clock waveform on PB0 is now output correctly at the expected frequency (2.4MHz).


This suggests a potential issue with the original GPIO pin PC2_C. Could this be due to accidental ESD damage to PC2_C?
I would greatly appreciate your insights on whether this pin re-mapping approach is feasible for long-term use, or if there are better ways to diagnose/recover the original pin functionality.
