FDCAN Tx Buffer allocation

[MD_it]

Hello,

I am trying to understand the memory allocation for the FDCAN, I am using a nucleo H723ZG.

With the latest CubeIDE 1.18.1 I seem to be able to configure 32 TX Buffers and 32 TX FIFOs:

However the message RAM mapping in AN5348 - Rev 5 shows that there are only a maximum on 32 for both Buffers and FIFOs:

Is there a mistake in the MX interface that should not allow more that 32 of Buffers + FIFOs combined, or the memory mapping has 2 sections of up to 32 elements for both buffers and FIFOs?

 

Thanks,

Marco

[mƎALLEm]

Hello,

32 of Buffers + FIFOs combined.

Even HAL implements this assert in HAL_FDCAN_Init() that doesn't allow to have more then 32 of TxBuffersNbr+TxFifoQueueElmtsNbr:

assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));

I'm escalating the behavior to the CubeMx team.

Internal ticket number: 213460 (not accessible by the community users)

 

[mƎALLEm]

Hello,

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@mƎALLEm wrote:

Internal ticket number: 213460 (not accessible by the community users)

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Issue has been fixed on CubeMx V6.16

[cberg.1]

I've just updated CubeMx and have the opposite problem with CubeMx V6.16:

In my project, I had TxBuffersNbr = 1 and TxFifoQueueElmtsNbr = 1
This is not allowed anymore, with a message saying the sum of TxBuffersNbr and TxFifoQueueElmtsNbr must be equal (not lower than) 32