How to generate a phase-shifted PWM in asymmetric PWM mode?

[toto00]

Hi everyone,

I was just wondering how to configure two PWM Channels of TIM1 to generate two phase shifted PWM signals in asymmetric PWM mode as shown in the attachment.

I'm using a STM32F303 on a custom board with CubeMX and SW4STM32.

According to Reference Manual RM0316 OC1REF1 is triggered by CCR1 and CCR2 as compare values during up- and down-counting and respectively OC1REF2 by CCR3 and CCR4.

Theory all good but how on earth do I configure that in CubeMX? When configuring a TIM channel to asymmetric mode I can only set one CCR value. Do channels 2 and 4 have to be set to 'PWM Generation No Output' and Mode:'Asymmetric PWM' to set CCR3 and CCR4 in the CCR register or how does the timer know all the CCR values to work in asymmetric mode? (See attachment).

Has anyone succeeded to configure with this nice feature on STM32MCUs so far?

cheers

[waclawek.jan]

> According to Reference Manual RM0316 OC1REF1 is triggered by CCR1 and CCR2 as compare values during up- and down-counting and respectively OC1REF2 by CCR3 and CCR4.

I see no OC1REF1 nor OC1REF2 in RM0316.

> how does the timer know all the CCR values to work in asymmetric mode?

Have you tried

TIM1->CCR2 = value;

?

JW

[3dMat]

I know that this topic is quite old, but recently I had the same issue and this page was the first one in Google results, so it could be helpful for others.

Timer Counter Mode should be Center Aligned mode (I don't see any difference between 1-3 variants in this case). All channels should be configured as PWM generation, but channel 2 and 4 as No Output. Signal is generated on CH1 and CH3 outputs. In Parameter Settings all 4 channels should have selected Assymetric PWM1 mode.

[BrainsOnFire]

Just to clarify, channels 2 and 4 are the ones that shift channels 1 and 3 right? In other words, selecting the pulse on the "No Output" channels make the other channels go low on that instance of the duty cycle? I'm trying to configure 4 channels with the same frequency at different phase shift without any PWM overlapping (See Image).