Is there a bug in STM32CubeMX about SDIOCLK?

[XvSenfeng]

STM32f103vet6

It's in the manual that SDIO adapter clock (SDIOCLK = HCLK).

 

 

When HCLK is set to 72MHz, SDIO_CK is configured through the register SDIO_CLKCR bit 7:0(CLKDIV). When the bypass clock is not used, SDIO_CK=SDIOCLK/[CLKDIV+2], which should be the frequency division of 72MHz

But the default parameter in the code generated by STM32CubeMX is to divide 48MHz.

 

The two macros in the file stm32f1xx_ll_sdmmc.h are defined for 48MHz, and these two macros are used when calling the HAL SD Init function.

If used in this way, it will cause overclocking.

 

[TDK]

On the STM32F4 series, SDIOCLK can be max 50 MHz. I suspect the same restriction is on this family, but can't locate it explicitly in the reference manual.

 

[FBL]

Hello @XvSenfeng 

It is mentioned in the datasheet SDIO interface allows data transfer at up to 48 MHz in 8-bit mode and is compliant with SD Memory Card Specifications Version 2.0. Note that STM32CubeMX generate default configuration.

[XvSenfeng]

I think the problem here is that this macro definition is used in the HAL_SD_InitCard function called by HAL_SD_Init. 

The main purpose of HAL_SD_InitCard is to generate a series of commands for SD card initialization. This value cannot be changed by the user through the parameter, which will cause the clock to exceed the specified 400KHz.

Using the generated code directly will result in an inappropriate clock rate at initialization time.

 

[FBL]

Hello @XvSenfeng 

I guess the issue is linked to the definition of SDMMC_INIT_CLK_DIV. Could you try to update the value accordingly and make sure not exceeding 48MHz. This issue is not present in new products since we have dynamic solution.

 

#define SDIO_INIT_CLK_DIV ((uint8_t)0x79) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */