[Nucleo-n6570-q] About XSPI LR can't run in SYSB at 400MHZ when number of memory data lines set 8line

[bioak]

Hello, 

I'm learning about the STM32N6 LR and XIP examples and want to get hands-on with them. I've already set OTP124 to 0x8000.

 

If SYSB is configured to 400MHz, the number of memory data lines must be set to 1 line and disable "X_ICACHE_Init()" for the app to function.

 

However, if SYSB is set to 80MHz, the number of memory data lines can be configured to 8 lines  and disable "X_ICACHE_Init()", and the app still works.

 

I'm very confused by this result and wonder if anyone has encountered the same problem or knows what I should modify?

Thank you.