STM32G0 minimum ADC frequency

[GrahamAU]

I'm configuring an STM32G031, using the STM32CubeMX perspective in STM32CubeIDE.  I want to optimise for low power consumption.  My device uses the ADC and I see the ADC has a minimum acceptable frequency, 140kHz according to the data sheet (data sheet table 57, fADC must be at least 0.14MHz).

I've configured the clock so that SYSCLK = 2MHz (HSI 16 MHz oscillator, divided by 8).  The ADC clock is also shown as 2MHz.  That makes sense.

But in the ADC configuration panel, the only clock options I can select are "sync divided by 1" or "async divided by 1".  I expected to be able to select higher dividers, down to "async / 8" (which would be 250kHz).  I can't even select "sync/async divided by 2" (which would be 1MHz).  All those slower options are greyed out, and when I mouse over them there's a tooltip that says something like "prescaler does not respect fADC fmin fmax conditions" or something like that.

Is this a configuration error in CubeMX, or have I misunderstood how the minimum ADC frequency works?  I couldn't find any app note that discussed minimum frequency, although there are plenty discussing maximum frequency!

[Souhaib MAZHOUD]

Hello @GrahamAU 

Thank you for bringing this issue to our attention.
I will escalate the issues to our CubeMX team for analysis and tracked by the Ticket 199353 (for internal follow-up).

BR,

Souhaib

[Tesla DeLorean]

Can't you pace it at whatever rate you want via a TIM trigger?

The ADC clocking determines how it samples

[danielbathtub]

@Tesla DeLorean  Maximum Time allowed between ADC conversions is 100 uS(from the datasheet), so No you can't pace it as you like. And then you need to go and waste a valuable Timer.

@Souhaib MAZHOUD Any Update regarding this ?.I am having a similar issue . I don't understand why cube is limiting me to 2 MHz when the datasheet clearly says 140 kHz  ?. 

[GrahamAU]

Huh.  I didn't realise anyone had responded to this.  Maybe because I wasn't checking on Christmas Day!! :)

Surely the trigger frequency and the clock frequency are pretty much independent of each other?  Yes I often use a timer as a trigger, but that just sets the rate at which conversions start.  My question was really about the ADC clock frequency, which determines how long conversions take rather than how often they start.

@danielbathtub You probably already know this, and I realise it's not the problem you're looking to solve, but I think the "Trigger frequency" setting works around the 100us max-time-between-conversions limit, at the expense of a few more cycles for the first conversion in each sequence.

In the end I've had great success in my project using "synchronous div-by-1", having re-arranged how I manage my conversions.  It turned out system power consumption was optimised by having the conversion complete as quickly as possible.