[STM32H7] How to use SDMMC with MDMA

[MVerr.1]

Hello Community,

I'm working on a storage module using SDcard for my project. In my application I would like to read and write to the SDcard using the MDMA as indicated in the reference manual of my micro-controller. For now I have the SDcard working in 4-bit mode but using the CPU.

I use the STM32H757II on a PCB connected to a SDcard reader on the same PCB.

With CubeMX I generated the code that allow me to mount a FATFS on my microcontroller and I can create/open/write/read on file with no problem.

But my application needs to log a lot of data to the sdcard periodically, to free-up the CPU I would like to do the transfer using a DMA.

In the reference manual 58.5.7 MDMA request generation it is explained that the MDMA can control the SDMMC peripheral to start new transfer

"The internal trigger lines from the SDMMC allow passing direct request to MDMA controller

to enable successive transfers from/to different internal RAM addresses without CPU use. [...]

The event can trigger the clearance of the DATAEND and CMDREND

flags and, eventually, a new transfer start, through MDMA direct access to the SDMMC

control and configuration registers, thus without CPU intervention."

However in CubeMX I don't seem to be able to link the SDMMC to the MDMA. I don't know either how to link an event of the SDMMC to trigger a change in configuration of those register with the MDMA.

How can I adapt what I have to use DMA instead of CPU.

How do you start a MDMA transfer to write on SDcard ?

Cheers,

Maurin

PS:

STM32CubeIDE Version: 1.3.0

STM32CubeMX Version: 5.6.0-RC6

[Khouloud OTHMAN]

Hi @MVerr.1​ ,

Let me first welcome you to STM32 Community:smiling_face_with_smiling_eyes:

If I well understand your question, you're asking about the STM32CubeMX feature in order to use MDMA requests to transfer data from/to SDMMC. Please correct me if I misunderstood.

To Configure SDMMC1 MDMA requests through CubeMX, firstly enable the SDMMC1 by selecting one of the available modes. Then select MDMA and Add Channel, a transfer request will be created by default, you can select one of the available MDMA events from the drop down list. You can add later the requests you needs for your project and configure them according to your requirements.

Hereafter a screenshot to clarify more the process:

 

Hope this answers your question.

Khouloud.

[MartinH1]

I have read  the Application note to get started with STM32H7 Series SDMMC host controller
I have a 1Bit connection of a SD Card with an STM32H725

It mentions checking a specific condition in line 2973 of the file ff.c.

The code snippet checks if a certain value is loaded correctly in the variable "win" at a specific memory location. If the value is not as expected (0xAA55 in this case), it returns 3.

It seems that the issue is that the variable "win" is not being fully loaded and the offset 510 is always 0. This could indicate a problem with loading or writing data to the memory area referenced by "win."

 

[MVerr.1]

Hello Khouloud,

Thank you for the reply.

I would like to be able to on the SDcard using a DMA instead of the CORE_M7.

As I understood they are two solutions. One includes configuring the MDMA as you suggest and the other one is by using the IDMA of the SDMMC. What is the difference between the two solutions ? Also, after configuring everything like you mention, how can I start transfering data using the MDMA ?

[Khouloud OTHMAN]

Hi @MVerr.1​,

Thanks for your feedback and sorry for my late reply.

By my previous reply, I have tried to explain briefly the steps to configure SDMMC MDMA requests through STM32CubeMX GUI. Here is Application note to get started with STM32H7 Series SDMMC host controller with much more details and explanations.

You can also find multiple examples through Example Selector in STM32CubeMX developed to be a good start point for your project:

 

Hope this helps you.

Khouloud.

[Hal56-GCI]

Unfortunately the document you reference leaves out some very important information.

 

Below is page 16 from the referenced document. It leaves off explaining how to fill in the data farther down.

 

Page 16

Once the dialog box is open, the user clicks on the Add a channel button and selects SDMMC1 end of data. Now the user can configure the MDMA for the data transfer (buffer transfer length, data alignment, source and destination). See the figure below for an example of the dialog boxes that the user finds when doing this configuration. Figure 14. MDMA end of data configuration with STM32CubeMx

 

 

How are these items to be filled out??

 

[Zed]

First of all, thank you very much to all of you, who clarifies these questions.

Personally, I stuck at the point of implementing MDMA transfer from AXI_RAM to DTCM_RAM.

How should I modify standard ST's µSD_DMA_FreeRTOS template to be able to use MDMA?

Again, DMA is working perfectly in my Project, but I want to send data that was read with IDMA and stored in AXI_RAM to DTCM_RAM. Manuals say that it is possible. All settings in CubeMX were made. But what next?

Any help would be appritiated!

THX!

[mayur_rajput]

hello @Hal56-GCI, @Hal56-GCI,
im having issue using sdmmc1 + mdma + fatfs + freertos can you please guide me what am i doing wrong, i have attached ioc and main.c files for referance.

[bramble]

Hi @mayur_rajput ,

What's the problem? It would help if you can summarise your configuration rather than expecting everyone to digest your ioc file, which without other code might not be enough to resolve your problems.

In my experience key things that can cause difficulties are:

• If you have data cache enabled, then you MUST ensure that your SD driver (BSP-specific driver implementation) has correctly enabled DCACHE management.
• Check also that your driver has enabled correct alignment for the scratch buffer that's used for DMA transfers.
• Check your compiler optimisation level. Level 03 on CM7 WILL DEFINITELY compile incorrect code*** in (at least some versions of) ff.c, resulting in Hard Fault exception due to misaligned transfer in the two functions shown below. If you see this Hard Fault, then you can either modify the function or add a compiler directive to compile those functions at O0 (maybe O1/2 will be OK, but I use O0 for them).   ***When I say incorrect code, I mean it generates assembly language instructions that are optimised without regard to the possibility that a pointer is not word aligned. It's logically correct but will hard fault on the ARM core.

static
WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
{
	WORD rv;

	rv = ptr[1];
	rv = rv << 8 | ptr[0];
	return rv;
}

static
DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
{
	DWORD rv;

	rv = ptr[3];
	rv = rv << 8 | ptr[2];
	rv = rv << 8 | ptr[1];
	rv = rv << 8 | ptr[0];
	return rv;
}

•  I'm assuming that your hardware is fundamentally OK and also your IOC config, but that's a whole load of other stuff for you to double check if you haven't already.

Good luck with this!