STM32N6570-DK: Missing Support for USB PHY Clock Sources

[bureau]

This thread is split from this old discussion

@FBL 

RCC_USBPHY1REFCLKSOURCE_OTGPHY1 and RCC_USBOTGHS1CLKSOURCE_HSE_DIV2 are missing in generated code

I created a simple FSBL application that is jump to the Appli
The Appli is using the same approach (SW solution) like it was implemented inside "Ux_Device_CDC_ACM" example, (it was migrated in to the Appli)
Currently, during debug, I am observing the same issue like it was described before (stuck in USB_CoreReset() during checking the "USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST" )

The solution, that you provided, it looks like it does not working anymore by using the latest Cube_FW and generated compilation errors (no defines for the RCC_USBPHY1REFCLKSOURCE_OTGPHY1 and RCC_USBOTGHS1CLKSOURCE_HSE_DIV2).

Could you please provide a solution (it would be better to see an example) how to solve this issue base on the latest MXCube and STM32CubeIDE versions. Currently it is :

• STM32CubeIDE_2.1.1 
• STM32Cube_FW_N6_V1.3.0

 

[FBL]

Hi @bureau 

Would you share your firmware ? PHY Reference clock setup is missing for N6 in HAL/LL and MX code generated. The issue is already escalated to dev team under this number CDM0055544 (just for internal use).

[bureau]

@FBL 

By "firmware" --  do you mean a BIN file (FSBL and Appli, or just for the Appli )?

The code that was generated by MxCube:

void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{

 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 if(pcdHandle->Instance==USB1_OTG_HS)
 {
 /* USER CODE BEGIN USB1_OTG_HS_MspInit 0 */

 /* USER CODE END USB1_OTG_HS_MspInit 0 */

 /** Initializes the peripherals clock
 */
 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
 PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT;
 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /* Enable VDDUSB */
 HAL_PWREx_EnableVddUSB();
 /* USB1_OTG_HS clock enable */
 __HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
 __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();

 /* USB1_OTG_HS interrupt Init */
 HAL_NVIC_SetPriority(USB1_OTG_HS_IRQn, 7, 0);
 HAL_NVIC_EnableIRQ(USB1_OTG_HS_IRQn);
 /* USER CODE BEGIN USB1_OTG_HS_MspInit 1 */

 /* USER CODE END USB1_OTG_HS_MspInit 1 */
 }
}

 

The code that I used during testing

void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{

 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 if(pcdHandle->Instance==USB1_OTG_HS)
 {
 /* USER CODE BEGIN USB1_OTG_HS_MspInit 0 */

 /* USER CODE END USB1_OTG_HS_MspInit 0 */

 /** Initializes the peripherals clock
 */
 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
 PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT;
 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /** Set USB OTG HS PHY1 Reference Clock Source */
 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
 PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1CLKSOURCE_HSE_DIRECT;
 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /* Enable VDDUSB */
 HAL_PWREx_EnableVddUSB();

 __HAL_RCC_GPIOA_CLK_ENABLE();

 /* Reset USB peripherals and configure the HSE clock */
 RESET_USB_MACRO(); // LL_AHB5_GRP1_ForceReset(0x00800000); \
 __HAL_RCC_USB1_OTG_HS_FORCE_RESET(); \
 __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET(); \
 LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(); \
 LL_AHB5_GRP1_ReleaseReset(0x00800000); \

 __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); // LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG1)

 /* Required few clock cycles before accessing USB PHY Controller Registers */
 HAL_Delay(10);

 USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4); // 19.2 MHz
 /*Set the PHY reference clock speed to 24 MHz */
 USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
 (0x2 << 4) |
 (0x1 << 2) |
 0x1U;
 
 __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET(); // LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY1);
 HAL_Delay(10);
 __HAL_RCC_USB1_OTG_HS_RELEASE_RESET(); // LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1)

 /* Peripheral PHY clock enable */
 __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE(); // LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1)
 
 /* USB1_OTG_HS interrupt Init */
 HAL_NVIC_SetPriority(USB1_OTG_HS_IRQn, 7, 0);
 HAL_NVIC_EnableIRQ(USB1_OTG_HS_IRQn);
 /* USER CODE BEGIN USB1_OTG_HS_MspInit 1 */

 /* USER CODE END USB1_OTG_HS_MspInit 1 */
 }
}

 

 

[bureau]

@FBL  
@Andrew Neil

As development board I am using NUCLEO-N657X0-Q
https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html

[FBL]

Hi @bureau 

For the USB PHY reference clock, the current support is still only accessible through low level register access.

So you can just omit this part:

PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1CLKSOURCE_HSE_DIRECT;

As of now, this configuration is not sufficient to fully configure the PHY reference clock. HAL/LL support is missing.

You still need to keep the USB PHY controller register configuration via low level access, and avoid duplication.

/* Set the PHY reference clock speed to 24 MHz */
USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
 (0x2 << 4) |
 (0x1 << 2) |
 0x1U;

  

[bureau]

Hi @FBL 

By suggested expression:

/* Set the PHY reference clock speed to 24 MHz */
USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
 (0x2 << 4) |
 (0x1 << 2) |
 0x1U;

afterwards we have 0x03 value inside "FSEL[2:0]: Frequency selection" field which is wrong in my opinion

Explanation:

The default value after the reset, for the "FSEL[2:0]" is 0x01. By applying " |=(0x2 << 4) " --- we have 0x03 which is not defined by the  RM0486 Rev 3
  

[bureau]

@FBL Is it correct that so many registers (see image, marked as yellow) has been cleared after execution of 

 /* Core Soft Reset */
 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;

 ?

Currently, my source code looks like:

void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{

 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 if(pcdHandle->Instance==USB1_OTG_HS)
 {
 /* USER CODE BEGIN USB1_OTG_HS_MspInit 0 */

 /* USER CODE END USB1_OTG_HS_MspInit 0 */

 /** Initializes the peripherals clock
 */
 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
 PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2;
 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /* Enable VDDUSB */
 HAL_PWREx_EnableVddUSB();
 /* USB1_OTG_HS clock enable */
 __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); // RCC->AHB5ENSR
 __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE(); // RCC->AHB5ENSR

 /* USB1_OTG_HS interrupt Init */
 HAL_NVIC_SetPriority(USB1_OTG_HS_IRQn, 7, 0);
 HAL_NVIC_EnableIRQ(USB1_OTG_HS_IRQn);
 /* USER CODE BEGIN USB1_OTG_HS_MspInit 1 */
 /* Reset USB peripherals and configure the HSE clock */
 RESET_USB_MACRO();
 
 HAL_Delay(10);
 USB1_HS_PHYC->USBPHYC_CR = 0x10025; // 1: The VBUS valid comparator is powered down. The session valid comparator is ON (default)
 // 010: 24 MHz
 // 1: PHY clocks are off during Suspend and Sleep mode. PLL is off.
 // 1: Retention mode disabled (default)
 
 __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();

 /* Required few clock cycles before Releasing Reset */
 HAL_Delay(10);

 __HAL_RCC_USB1_OTG_HS_RELEASE_RESET();
 /* USER CODE END USB1_OTG_HS_MspInit 1 */
 }
}

 

[FBL]

Hi @bureau 

I assume it gets cleared after calling reset macro.

RESET_USB_MACRO();

Let me check and will get back to you by tomorrow. I need to check updates with development team. Thank you for your understanding. 

 

[bureau]

@FBL 
No, it is cleared after call of 

/* Core Soft Reset */
 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;

which is inside 

USB_CoreReset()