What is the significance of SRAM Bank swapping?

[Aarra.1]

Hello all,

While configuring the FMC SRAM configurations for STM32H747 MCU I found the option for bank swapping.

As I see the reference manual I understand that the chip select configured interchanges it's address with that of the SDRAM bank addresses.

And I did face an issue to read and write from the SRAM but when I enabled the bank swap option in the cube MX now my SRAM responds correctly.

Kindly help me out in understanding the role of BANK SWAPPING here.

Thank You!

[Ghofrane GSOURI]

Hello @Aarra.1​ 

First let me thank you for posting.

In the context of SRAM configurations for microcontrollers like the STM32H747, bank swapping refers to the ability to swap the memory map between two or more memory banks, typically for the purpose of allowing more efficient access to memory.

When a microcontroller has multiple banks of SRAM, bank swapping allows the programmer to access different banks of SRAM as if they were contiguous blocks of memory, even though they may physically be located in different areas of the chip. This can be useful when working with large data sets or when multiple tasks need to access different areas of memory simultaneously.

In the case of the STM32H747, enabling bank swapping may have resolved your issues with reading and writing from the SRAM because it allowed the microcontroller to access the correct bank of memory when accessing specific addresses. Without bank swapping enabled, the microcontroller may have been attempting to access the wrong bank of memory, resulting in errors or unexpected behavior..

BR,

Ghofrane

[Aarra.1]

Hello @Ghofrane GSOURI​ ,

Thank you for your response.

[FBL]

Hello @Aarra.1​ 

It depends on your application, are you enabling the cache for example?

Enabling the SRAM bank swapping allows to access the SDRAM banks at two different addresses mapping. So, it is possible that accessing normal memory should solve your issue.

You may refer to the datasheet and the reference manual RM0399 Table 6. Memory map and default device memory area attributes.

Hope this helps!

Firas

[Aarra.1]

Hello @F.Belaid​ 

Thank you for your response.

Yes my cache is enabled im using LWIP for ethernet communication.