STM32 MCUs Products

Hi everyone,This is a follow-up to my previous question about LED behavior on the STM32H755ZI-Q when using OpenAMP communication between CM4 and CM7.https://community.st.com/t5/stm32-mcus-boards-and-hardware/nucleo-h755-led3-not-turning-on-pb14-in-ipc-example/td-p/829379 While debugging why LED3 on PB14 was not turning on (assigned to CM7), I found a very unusual issue in the CM7 startup code generated by STM32CubeMX.CubeMX generates the following D2 domain clock readiness loop:timeout = 0xFFFF; while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET) && (timeout-- > 0));If I rewrite the loop explicitly:while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET)) { timeout--; if (timeout < 0) { Error_Handler(); } }then PB14 suddenly starts working normally.But here is the strange part:If I add any variable initialization before the loop, for example:timeout = 0xFFFF; while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET)) { timeout--; if (timeout < 0) { Error_Handl

Hello ST experts,I have a weird experience with UART communication between two STM32G4 microcontrollers. MCU1 sends 10 bytes to MCU2 via UART. Both UARTS are configured with 9600 Baud rate with DMA in circular mode. The Problem arises when the MCU1 is turned on, it sends 11 bytes which the first byte is 0x00 in case I need only 10 bytes to be received. Can you help me in this issue?Best,Davood.

Hi, everyoneI recently encountered a strange phenomenon. I opened three DMA channels on the STM32G474RBT6.The first one is Channel 1 of DMA1 (circular mode), which is used for automatically collecting the data converted by ADC.The second one is channel 8 of DMA2 (normal mode), which is used to transfer the calculated data to the timer for updating the PWM.The third one is Channel 1 of DMA2, which (normal mode) is used to send serial port data of variable length. The first two did not enable the interrupt service function.But if the DMA in the third case does not enable the interrupt, the serial port sending process will be stuck (the HAL library shows that the DMA2channel1 is in the “BUSY" state). If the interrupt is enabled, this situation will not occur.However, the interrupt service of the first two I didn't enable DMA can still run normally. The data of the ADC can be automatically transmitted, and the timer can also send out the correct PWM signal. The priority of DMA has already

In my embedded software project, I need to write a bootloader. I wrote an application code for the bootloader and testing, and everything is fine so far, but the delay function in the application code is not working. I think the reason for this is the Vector Table. I wrote the vector table to the RAM address, but it didn't work at all. It jumps to the application code, turns on the LED, but does not toggle. I would really appreciate your help. (STM32f030c8t6 board)#define APP_START_ADDRESS 0x08006000 // User application start address #define APP_START_ADDR 0x08006000 #define SRAM_BASE_u 0x20000000 #define VECT_TABLE_SIZE 0xC0 // 48 vectors * 4 bytes void JumpToApplication(void) { // 1. Dsiable all interrupts __disable_irq(); // 2. Deinit HAL and RCC (optional if bootloader did init) HAL_DeInit(); HAL_RCC_DeInit(); // 3. Copy vector table memcpy((void*)SRAM_BASE_u, (void*)APP_START_ADDR, VECT_TABLE_SIZE); // 4. Remap SRAM to 0x00000000 SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_

I am designing a system that will utilize the dual bank feature of the STM32 devices to make a robust system for OTA updates. I am currently using a STM32U545 for my project and have questions about writing to the FLASH_OPTR to change the SWAP_BANK bit.My setup has an external microcontroller connected to my STM32U545 that interfaces through UART and has control of the BOOT0 pin and the RST pin of the STM32 device. I was confused by the statement in the AN3155 pg. 20 when it talked about the Write Memory command and said "If the Write Memory command is issued to the option byte area, all bytes are erased before writing the new values, and at the end of the command the bootloader generates a systemreset to take into account the new configuration of the option bytes". What does it mean by all bytes are erased? My current plan was to use the read memory command and read the register FLASH_OPTR at 0x4002 2040 and then read bit 20 of that register(SWAP_BANK bit) then perform an operati

Hello, We are facing an intermittent CAN-FD issue in the field and would appreciate guidance from the community. Our system has two devices on the bus (no other device on the bus) using a request–response architecture. The master sends a request every 30 ms and the slave responds. This setup is deployed in hundreds of units running continuously (24 hours). Out of these, around 3 to 5 units per day show acknowledgement errors, which we track through the CAN protocol error counters. The behaviour is unusual: • The issue appears randomly on any unit.• No bus-off condition is ever reported.• Despite no bus-off, communication between the two nodes temporarily stops.• Communication recovers automatically after a few seconds without any intervention. Initially, we suspected a physical wiring problem. We re-checked all connectors and even secured them with glue. The bus has 120-ohm termination at both ends. However, the issue still appears randomly. Below are the system details: Microcontrolle

Hello,I have not found the maximum TRACECLK frequency of the STM32H725 in the documentation. It looks like it is generated by PLL1 with flexible division ratios and thus can attain values that are not realistic for I/Os (100 to 220 MHz for Speed 11 and 2.7 V ≤ VDD ≤ 3.6 V as per p.165 of DS13311).Is the maximum TRACECLK set by the maximum I/O output frequency or is it restricted to another value? Regards,Bernd

I am having a custom board having STM32N657I0H3Q interfaced with quad flash MX25R6435FM2IL0. I am unable to access (both read and write) to the flash MX25R6435FM2IL0.I have attached Saleae capture (configured the flash in single mode only for Saleae capture). Also, debug log of EMM running in FSBL.The eval board (DK board) is having MX66UW1G45G doing good. The logs looks like EMM could not access the SFDP structure.  

Hello, I am reading 6.3.30 LCD-TFT controller (LTDC) section to interface with DS90C385A (LCD) or ADV7125 (VGA) Assume that LCD Clock (pixel clock) polarity is set to high. Ideally, we can expect rising edge of clock aligned to the middle of the data.  But I can see there is a more time for setup and less time for hold. Refer the figure 46 of datasheet.      Note: I am going configure pixel clock low for DS90C385A (LCD) and high for ADV7125 (VGA).  Also, I need to ensure HW work till 150MHz clock.       

Hello, How to perform dual-core communication on STM32H747?

There is this errata for STM32G0B12.2.10 Prefetch failure when branching across flash memory banksDescriptionIn rare cases, the code prefetch may fail upon branching and function calls across flash memory banks,regardless of the DUAL_BANK and nSWAP_BANK option byte settings. The failing prefetch then provides anincorrect data to the CPU, which causes code execution corruption and may lead to HardFault interrupt.The workaround is obvious, either disable prefetch when jumping to code in the other bank and enable it again afterwards or use a small "trampoline" function in RAM. We can live with that, as our software is split into separately compiled "core" and "application" parts loaded into separate banks, having only a handful of interface functions there would be e.g. no jumps into library functions in the other bank. What about exceptions and interrupts, how are they affected? The ARM literature generally refers to loading the exception handler address from the vector ta

I have seen that it takes about 28 ticks to read registers, so I think my stm32h750 runs really at 17Mhz, it seems is not risk, so perhaps it exists another more fast stm32 micro that have more 17 MIPS 

This is a pretty basic question but I would like a bit of clarity if possible.If a GPIO pin is configured for the fsbl code can it also be used in the Appli code?If so how would you go about defining it in the Appli code? There doesn't seem to be an option to use a GPIO pin in both fsbl and Appli in STM32CubeMX or do you have to configure it manually in the Appli code?

Our company has a chip that outputs data via DCMI, though it does not employ a standard DCMI interface. It lacks a horizontal synchronisation signal, possessing only a vertical synchronisation signal. Could you advise which chips are capable of receiving such data? If available, please provide specific chip models and concrete code examples.   Edited by ST moderator: This post has been translated from Chinese to comply with the ST Community guidelines.

Using Nucleo-U545RE-Q, SPI2 Full-duplex Master, default GPIO selected by STM32CubeMX v6.15.0 with LL selected for implementation.Config clock for max 160 MHz and prescale SPI by 8 for 20 Mbps. Add GPDMA Ch2/3 for SPI2 TX/RX.I double checked the output configuration code generated by the CubeMX against the Cube_FW_H5_V1.5.0 Examples_LL: SPI_TwoBoards_FullDuplex_DMA_Master_Init, and it matches exactly but for peripheral selection. Jumper-wire PC1-to-PC2 (CN7.36-to-CN7.35) for simple SPI loop-back test. With this configuration, the loop-back works when I implemented the SPI full-duplex transfer by LL blocking code. But trying to use the GPDMA channels results in no data, no DMA IRQ for TC or DTE, no SPI IRQ for anything. Below is the simple code to try to get a transfer going, there is initialization code that enables all SPI and DMA interrupt sources and handles the IRQ by clearing the flag and setting the local global booleans that you see below. Note that this is setup f

Hi,I have a custom board with an STM32L031C6 and I'm trying to read the internal temperature. The board is battery powered at about 2.6V and the vdda is the same.If I read the ADC channel with vrefint, it returns a value of about 850, which, when passed to the function __LL_ADC_CALC_VREFANALOG_VOLTAGE(adcVal[4], LL_ADC_RESOLUTION_12B), returns a calculated VDDA of 6V, which is obviously incorrect.Using this vref to calculate the internal temperature obviously results in a value that's out of range.The same thing works correctly on a NUCLEO-C031.What am I doing wrong?Thanks!

Hello,I configured TIM1 as shown in the attached image: Everything works as expected I am controlling an inductive load which oscillates heavily after the PWM is turned off. I therefore decided to immediately short the low-side MOSFET (CH1N) to ground if a BREAK or BREAK2 signal is received. I set the Channel Idle State to SET. And the behavior of BREAK/BREAK2 changed.As seen in the close-up:: A low state on BK2 does not set a high state on CH1N. Should BK1 and BK2 not be ORed?

Hello ST Support Team,I'm working with the STM32L031K6U6 (32-pin UFQFPN package) and need clarification on ADC channel mapping.Question: Is there an ADC Channel 9 available on the STM32L031K6U6, and if so, which physical pin does it map to?Context:- I'm trying to use PB1 as an ADC input- Documentation suggests ADC Channel 9 should be availableCould you please confirm:1. Which pins have ADC capability on STM32L031K6U6 32-pin package?2. Is ADC Channel 9 available on this specific package variant?3. If ADC Channel 9 exists, which physical pin does it connect to?Hardware: STM32L031K6U6 (32-pin UFQFPN package)IDE: STM32CubeIDEHAL Version: LatestThank you for your assistance.

Hello, I expect this to be flagged before but couldnt find during search. Is Table 116 for the stm32f43xx on page 768 missing registers for CRYP_K2LR / CRYP_K2RR at offset 0x30? TIA

Posted on November 05, 2012 at 11:28Revision 2 of RM0090 is available. http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/DM00031020.pdf JW

Hello All,   I am using the STM32H757I-EVAL for one of the development project for Touchgfx, 1) When-ever I am loading/debugging the project using STMCUBEIDE, only in System Mode I am able to detect the Board, but not in Flash mode. 2) With STMCubeProgrammer, I have to connect the device in System Mode, then I have to Erase the Internal and External Flash, then disconnect the Board and Bring the Device in Flash Mode and then Flash the code. Till now I am able to run the Program, But as soon as I disconnect the usb (stlink), The Previously loaded program supposed to run as the mode is still in flash, but I can see anything on screen.  Could anyone please let me know the correct way to do it ? I mean I don't have to load or flash code again and again to test. The program should load from Flash after power ON- OFF-ON.  Just for info 34757228 is the size of the program.

I got a hard time comprehending about the two interrupt lines in the manual. I can really see a "connection" between certain sources to the interrupt lines, nor can i find a register to connect them. It seems to me, that i only can decide what interrupts will fire, and what interrupt line they will go to then. But i cant think of, how i could have both interrupt lines running in paralell. I think i missed something. Is there a better information about this out there?

Hi there! I'm looking to interface a dual channel 12bits ADC (TI ADS4222) with an STM32N647L0.Using a 58MHz sampling clock, I will generate two 58MSPS data streams feeding into my STM32. The acquisitions will be short, so the raw data will be around 1 MB per channel.I'm wondering whether I can use both the DCMI and DCMIPP interfaces simultaneously to handle the two ADC channels and feed the NPU.Has anyone already tried this? What is the maximum pixel clock for each interface? I'm not sure which application note applies to these devices. Thanks for your help Quentin

Hello,I am working on a custom mixed communication implementation using USART in single-wire half-duplex mode with TX-only operation, level inversion, and interrupt-driven transmission on an STM32G0B0 (RETx package).During testing, I observed the following behavior:When the USART is configured in CubeMX as Single Wire (Half-Duplex) with TX inversion enabled and the line is internally pulled up, no data is transmitted.However, when using asynchronous mode with the same inversion settings, transmission works normally.My questions are:Is this behavior expected when using USART Half-Duplex mode with level inversion and a pull-up on the line?Has anyone experienced this behavior on the STM32G0 USART peripheral?I plan to use USART3, USART4, USART5, and USART6 simultaneously under an RTOS environment, all configured the same way (single-wire, inverted signal, interrupt driven). Under these conditions, should I expect similar transmission issues on all USART instances?All selected pins support

Hello, I wrote a program to test the CAN bus.In its current version, I am using standard CAN at 1 Mb with 8-byte frames.I transmit 16 frames with a 5 ms delay between each transmission.To identify the last frame in the block, I send a frame with a zero data length I am facing several issues. When I configure the CAN bus in INTERNAL_LOOPBACK mode, if I do not enable automatic retransmission, some frames that are reported as successfully transmitted are not received. In NORMAL mode, no frame is flagged as an error on the transmitting Nucleo board, but some frames are never received on the receiving Nucleo, while others are received multiple times. The last issue is that I can only communicate up to 4 Mb. At 8 Mb, transmission and reception errors are reported.