STM32 MCUs Products

Hello, I'm using two H533 Nucleo Boards and I'm trying to establish an I3C communication between them. There are no specific examples for this protocol using two of these boards, instead there are only examples for a sensor which I don't have. So, I tried to copy the example presented in Introduction to I3C for STM32 MCUs Application Note. This did not work. Also, I tried to adapt the example for the H503 called I3C_Target_ENTDAA_IT, copying the main.c. Also didn't work. The Target is not ack when sending 7E.On the controller side, I'm just trying to send this:if (HAL_I3C_Ctrl_DynAddrAssign_IT(&hi3c1, I3C_ONLY_ENTDAA) != HAL_OK){Error_Handler();}On the target side, this is my code:/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file I3C/I3C_Target_ENTDAA_IT/Src/main.c * @author MCD Application Team * @brief This sample code shows how to use STM32H5xx I3C HAL API to * manage a Dynamic Address Assignment pro

Hello,I’m currently working with I3C communication using STM32H7S3L8 and encountered a case where the controller (master) sends a read request, but the target either does not respond or sends no data. This section explains: How to distinguish a NACK caused by an invalid address(target absent) from a situation where the target is present but hasn't provided data. How to ensure the controller receives 0x00 when the target has nothing to send.thanks in advance for your contributions!

Hello ST Community,I am working with STM32H750VBTx on STM32CubeIDE. I use UART7 + DMA with HAL_UARTEx_ReceiveToIdle_DMA()to receive responses from a GSM modem.Problem:- GSM responses are stored in my gsm_response_buffer[] incrementally- For example: first "RDY", then "AT OK", then "ATE0 OK" → all get appended- I expected each new DMA reception to start at buffer[0]. Debug screenshots are attached.Could you please advise how to properly useDMA reception so each new response starts fromgsm_response_buffer[0]?Thanks in advance!Refer the code in the Test_GSM.c file also if needed in the main.c file i call```c /* USER CODE BEGIN 2 */ #if (ENABLE_006_GSM_Folder == 1) HAL_UARTEx_ReceiveToIdle_DMA( &huart7, gsm_response_buffer, GSM_RESPONSE_BUFFER_SIZE ); __HAL_DMA_DISABLE_IT(&hdma_uart7_rx, DMA_IT_HT); #endif``````c /* USER CODE BEGIN 0 */ void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { if(huart->Instance == UART7){ HAL_UARTEx_ReceiveToI

Hi We are developing a new product based on the STM32U073CCT6 MCU and STM25DV-I2C tag. Question:Is it possible to update the STM32 firmware through the NFC tag? If so, can you provide a sample code?BRGilberto 

Hello everyone, I'm reaching out to seek guidance in pushing the SPI CLK line output to, at least, 65 MHz.In theory, this should be possible according to the Reference Manual by setting the GPIO speed to Very High in Vdd = 3.3. Currently, I am able to drive the signal at 40MHz and still get a decent square signal with a bit of over and undershoot, however, pushing above these speeds causes signal degradation and distortion. The rise/and fall times for the wave seem to be too slow, causing further problems. I've tried enabling the cell compensation with a sequence similar to the one below as per the Reference ManualRCC->CR |= RCC_CR_CSION; // turn on CSI while(!(RCC->CR && RCC_CR_CSION_Msk)); // wait for the CSI to come online SBS->PMCR &= ~(SBS_PMCR_BOOSTEN); SBS->PMCR |= SBS_PMCR_BOOSTVDDSEL; // reduce harmonic distortion SBS->CCCSR |= (0 << SBS_CCCSR_COMP_CODESEL_Pos) | SBS_CCCSR_COMP_EN; while(!(SBS->CCCSR & SBS_CCCSR_COMP_RDY

Hello!Can I use 'TRGO2' event signals from Advanced Timers (1,8,20) as event sources for Slave Timers? The Reference Manual (RM0440 Rev 9, p. 381), the Internet, CubeMX and Google - all say "Yes", but in practice I could not use them for Slave Timers. I only found in one document that it is not allowed and now I do not understand whether it is true or not. Thank you.

Hello!I have a new project with a STM32F407VET6 and a STM32F103xxx over a RJ45 Jack with I2C.i worked a lot of time with I2C EEPROMs and it works fine, but my communication between the 2 STM's are horrible, or i am too confused.i found the tutorial on https://controllerstech.com/stm32-as-i2c-slave-part-1 in this tutorial, has the Slave the Address 0x12 (without shifting <<1) the code of the master:   /* USER CODE BEGIN 2 */ uint16_t slaveADDR = 0x12<<1; uint8_t TxData[6] = {0x1, 0x2, 0x3, 0x4, 0x5, 0x6}; while (1) { HAL_I2C_Master_Transmit(&hi2c1, slaveADDR, TxData, 6, 1000); HAL_Delay (1000); }  okay, here are the address shifted, but my slave are not receiving data on 0x24.my logic analyzer says, the master sends data to the address 0x24 (it's shifted.. <<1) and not to 0x12. I used the function HAL_I2C_IsDeviceReady(), but i am wondering, in the description of this function are no comments like "shifted address" or an

I'm attempting to implement a USB MSC Device using the USB_OTG_HS on a STM32U5A9J-DK1. I'm using the STM32CubeMX version 6.14.1 and STM32Cube_FW_U5_V1.7.0 to create a USBX stand-alone (without THREADX) MSC device. The project builds and runs, with successful initialization of the USBX device subsystem. However, connecting to a host does not trigger the OTG_HS_IRQHandler() interrupt. A couple of questions:A call to MX_USB_OTG_HS_PCD_Init() is generated in main by CubeMX, but I don't find anywhere in the code where PA11 and PA12 are initialized to the USB_OTG_HS alternate functions.Since enabling VBUS Sensing via PA9 is not an available option for this device in the CubeMX, and I see from the schematic that VBUS_SENSE is connected to PG1, I'm not at all clear how connection to a host is detected to fire the USB_OTG_HS interrupt.The STM32Cube_FW_U5 only contains examples for USBX Host, so I'm not sure where to look for guidance.   

Hello,To protect the device's software, I am updating the RDP values in my own bootloader software, and to protect it in the event of a sudden power outage, I am also updating the BOR values. I am performing these updates only using HAL APIs. Additionally, I am writing the option bytes one by one. During development and testing, this worked flawlessly. However, the device has now entered serial production, and we are programming in large quantities. So far, 200 MCUs have been programmed, and approximately 50 of them ended up with an RDP value of 0xFF and the BOR value not set. I urgently need assistance regarding this issue. Production has been halted and is waiting for this problem to be resolved. Please help me.I am adding the code block where I perform this operation below.  /* USER CODE BEGIN 2 */ #ifndef DEBUG FLASH_OBProgramInitTypeDef ob_init; // Unlock Flash and Option Bytes HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); // Get current configuration HAL_FLASHEx_OBGetC

Hi everyone,Im currently trying to use SPI with DMA mode on STM32U031G6 with an S2LP,In this specific case I want to obtain the number of bytes present in my FIFO (10 bytes here), but the problem is that my reading through DMA mode does not work.Below is the data that I analyze in SPI using a logic analyzer : we have the read command (0x01) + the FIFO status command (0x90) + the command (0x00) where I get my response 0x0A or my 10 bytes. What I don't understand is that the read_1_registre_DMA function returns 1 on the 3rd data item that I want to read as below :Below is the function where I give my 3 Tx commands and where I expect 3 responses in return for Rx but the data is not correct for RX[2] (3rd element, or for me I should find my 0xA)://----------------------------------------------------------------------------- uint8_t S2LP_Read1Registre (uint8_t address) //----------------------------------------------------------------------------- { S2LP_Init_DMA_Mode(); // Pré

Hello,I am using STM32 microcontrollers on CAN FD ISO buses.The problem is that I am not able to configure CAN FD bus with a nominal rate of 500kbps and a data rate of 1Mbps. All others configurations are working as expected, see below all combinations tested:Nominal rate (kbps)Data Rate (kbps)BRS500500No5001000Yes5002000Yes5004000Yes5005000Yes5008000Yes10001000No10002000Yes10004000Yes10005000Yes10008000YesI tried the following issue on STM32G431KBU and STM32H723ZGI. CAN input clock is 80MHz, Sys Clk is 512MHz for H7 and peripheral clock is256MHz. On G4, Sys clock is 160MHz and peripheral clock is 160MHz. So on both microcontrollers CAN clock is lower than peripheral clock.Bit timings for nominal rates are the following:Nominal bitratePrescalerSJWTseg1Tseg2 Tq per bitTheoretical bitrate (kpbs)500162721050010008272101000Data ratesPrescalerSJWTseg1Tseg2 Tq per bitTheoretical bitrate (kpbs)50016472105001000827210100020004472102000 Any help would be appreciated,Best regards

What is the sequence and APIs to erase and program the Engineering bytes?There are APIs to handle Main flash, and APIs to handle OTP, but it is not clear how the Engineering bytes should be handled.Thanks

Greetings!I am using the STM32U031 with STM32CubeMX HAL as an SPI Slave and would like to receive data that has variable length (max 50 bytes). I am using software NSS and my current approach is to start a DMA Rx/Tx transfer (using HAL_SPI_TransmitReceive_DMA) of the maximum expectable length when NSS goes down (in the corresponding GPIO callback) and to abort the transfer when NSS rises again (using HAL_SPI_Abort). From a functional perspective this approach works, but the abortion of the Transfer currently takes about 1.4 ms (at 8 MHz MSI Clock). As a result,  the answer to the Master is not ready when it clocks again. Is there anything I can do better / different to improve the timing?I know that using HAL_SPI_Receive_DMA instead of HAL_SPI_TransmitReceive_DMA for Rx would reduce the time required for aborting the transfer, but then it seems that I have no control over the data that is transmitted while receiving, which causes trouble on the Master side

We have a working production firmware for the STM32H7B3 that uses a Winbond W25Q01JVZEIM external flash using QSPI in memory-mapped mode to store data and assets for a TouchGFX and other applications.Now, due to internal flash limitations, we are attempting to execute some code directly from the same external flash. As a starting point, we created a simple test function to run from external flash:__attribute__((section("ExtFlashSection"))) void test_ext_flash_func(void) { volatile int x = 1; x++; }The rest of the application continues to run from internal flash. However, when this function is called, the MCU enters a continuous reboot loop. We have added Hard fault handler but couldn't see any prints for different register values.Current ConfigurationLinker ScriptMEMORY { ... OSPI (xr) : ORIGIN = 0x93170000, LENGTH = 32M } SECTIONS { ... ExtFlashSection : { *(ExtFlashSection ExtFlashSection.*) *(.gnu.linkonce.r.*) . = ALIGN(0x4); } > OSPI }2. MPU

Hello, I am working on simple program to read ADC using the STM32u585QII microcontroller. I am using polling method in Scan mode on 4 channels. All set as 14 bit but understood the readin will be in 12 bit. The problem is the values I am getting are not reflecting the real value at the input. I am receiving something like  1586 cnts on 1st and 3rd channel and 2395 cnts on 2nd and 4th channel. Values make no sense assuming I have stable (verified with oscilloscope) voltage 1.61V. Vref is 2.5V external. Also when I am trying change voltage at the inputs the reading doesn't change. Can someone point me the possible issue with the configuration. /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software i

When the MCU is placed in Standby Mode, where does the CPU begin to execute when exiting the mode? (for example, on an RTC event)  Is it a reset or a return from interrupt?  RM0394 isn't clear on this. 

Hi all, I am trying to use FDCAN with Baud rate switch (500 kB / 2 MBit) activated and I want to send 64 Byte. Processor is STM32H7A3. Project was set up with CubeMX V. 6.11.1 and HAL FW_H7 V1.11.2. Clock for FDCAN is 80 MHz.   The problem is that the system only sends with 500 kB and 8 Bytes only. I am transmitting the data to my PC using a PEAK USB dongle (FDCAN capable with BRS) and in parallel check the messages on a scope.  I don't know, why it doesn't switch to 2 MBit and I only see  8 Bytes with 500 kBit on my scope and on PCAN-Explorer. Here my init and transmit code sequences: FDCAN_HandleTypeDef* phCan; phCan = &hfdcan1; phCan->Instance = FDCAN1; phCan->Init.Mode = FDCAN_MODE_NORMAL; phCan->Init.FrameFormat = FDCAN_FRAME_FD_BRS; phCan->Init.AutoRetransmission = ENABLE; phCan->Init.TransmitPause = DISABLE; phCan->Init.NominalPrescaler = 10; phCan->Init.NominalSyncJumpWidth = 1; phCan->Init.NominalTimeSeg1 = 11; phCan->Init.No

What is the difference between STM32F411VEH6U and STM32F411VEH6? What does the suffix U mean?

STM32L072 – LPTIM1 external pulse counting with LSE in STOP mode not workingDescription:Hello,I am trying to configure LPTIM1 on an STM32L072 to count external pulses from a button connected to PB5 (LPTIM1_IN1). The goal is to keep counting pulses while the MCU is in STOP mode.What I did:RTC is already running from LSE in STOP mode, so LSE is enabled and stable.In CubeMX I selected:LPTIM1 clock = LSE (ULPTIM)Counter source = ExternalGenerated initialization looks like this:hlptim1.Instance = LPTIM1;hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; // CubeMX output, even if I picked LSEhlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;hlptim1.Init.UltraLowPowerClock.Polarity = LPTIM_CLOCKPOLARITY_RISING;hlptim1.Init.UltraLowPowerClock.SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION;hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_EXTERNAL;HAL_LPTIM_Init(&hlptim1

I have written a custom bootloader that is running on a Nucleo-L433RC-P board. The application uses USB CDC to call the bootloader and the bootloader uses USB DFU to download the application. I wanted to use USB to call the custom bootloader, rather than having to use a physical switch on the BOOT0 pin to call the internal bootloaderI can successfully download a simple application which just flashes an LED using the USB DFU bootloader.However, when I download my actual project, it appears to download successfully but does not run.My actual project is more complicated and uses the following peripherals:RTCSPI2 and DAC1 (using DMA)SPI1TIM6TIM7I2C1I2C2USBShutdown and standby using WKUP and RTC wake sources I used the following guide to write the custom bootloader and simple application...https://stm32world.com/wiki/Custom_DFU_BootloaderThe following web tool is used to download the application...https://devanlai.github.io/webdfu/dfu-util/ I have spent days trying

Our STM32H745XIH microcontroller enters an infinite loop after updating the software with “Release” compilation flags (optimization enabled). This only happens with a specific build, and changing a single piece of code that is definitely not related to any hardware component can solve the problem (e.g., adding a single line such as int a = 45;). We believe the problem may be related to the watchdog reset, because when connected to the microcontroller via a debugger, it resets and starts working normally without any problems, the logic of our application works, and the device is fully functional. We thought the problem might be caused by the clock initializing too quickly, so we added a startup delay using: static void __attribute__ ((optimize("-O0"))) StartupDelay(void) { for(uint32_t i = 0x27614U; i > 0U; i--); } This seemed to solve the problem. However, after changing another part of the code, the problem started to reappear.RCC_RSR value: 4FE0000 No hardfault is observed before

I'm attempting to use a custom LCD daughter board designed to plug onto the STM32U5G9J-DK1 in place of the round display that comes with the DK1. The schematics for the DK1 have a note in read indicating that the DSI_CK_N and DSI_CK_P pins are reversed and that they should be swapped in software, and indeed the pin assignments on the schematics seem to agree with that note. The schematics for the round display board show those pins to be correct, i.e. not reversed. I have working example code for the round display, but nowhere in that code do I see that the DSI clock pins are reversed.There's a HAL function for doing this: HAL_DSI_SetLanePInsConfiguration(), and the DSI register that does the swapping is WPCR[0]. Nowhere in the working example project do I find any call to the function or any write to that register, so I'm confused as to how it could be working. Is the schematic not correct? Is there some other means of swapping the pins? Needless to say, my custom board is not working

Hi,My battery (++ LTO/Bucks) that runs everything on my PCBA is connected to VBAT (pin 1). Before the connection I have a voltage divider factor of roughly 1.374, but what I read on the pin via ADC1 channel 18 (what VBAT is routed to internally) seems to be non-sensical. With a battery voltage of 3.6V I measure roughly ~1160 mV (after multiplying by 4 and 1.374). When I tried replacing the resistors in my voltage divider by smaller ones I got higher measurement values.VBATEN is enabled in ADC12_COMMON_CCR. Also tried to enable MONEN in PWR_BDCR1, but that didn't make any difference.What's could be the issue here?

The errata for the STM32U575 series includes the following: We would like to use the first option of the 2 listed workarounds (the one that does NOT require disabling and reenabling the ICACHE).  Does ST have any implementation examples of this workaround? I am confused about why it is necessary to put the low-power entry code in a non-cacheable region.  We use a WFI instruction to put the MCU into STOP mode.  If we could ensure that the WFI was in the last 2 bytes of a 16-byte block of memory, would that fix the errata?  This way, the next instruction after WFI (and thus the 1st instruction executed outside of STOP mode) would be guaranteed to be in the next cache line.  In that case, would the WFI and preceding code need to be in a non-cacheable region? Thanks!

I have the STM32N6570-DK board, and I was able to execute the example from:- https://github.com/STMicroelectronics/STM32N6-GettingStarted-ObjectDetectionFollowing the steps provided in the workshop:- https://www.youtube.com/watch?v=29EUWNwfywI&list=PLTJzs51NlEICI7ARAHOyUqMhTgJE0UFv0&index=6- https://www.youtube.com/watch?v=VV9f5e3nqM4&list=PLTJzs51NlEICI7ARAHOyUqMhTgJE0UFv0&index=7---However, after I was able to execute it at first, I tried to convert my own model and modify the example just to execute my own Yolo model, just to execute the inference and perhaps get the inference time via UART.The conversion worked fine using the stedgeai (version 2.2) command; however, it didn't work on the board on the first try, which was expected.After a few failed tries, I removed all of my local changes and loaded the initial example binary, the "Model/STM32N6570-DK/network_data.hex" and the application binary again, using the board in development mode. To my surpri