STM32 MCUs Products

Hi all, I’m working on enabling USB High‑Speed (HS) communication on an STM32F446RE using an external USB3300 ULPI PHY, but I’m running into several issues and can’t get ULPI communication working. Current Issues: DIR pin stays high – it appears the STM32 never gains control of the bus. The ULPI clock runs at 60 MHz (derived from the USB3300’s 24 MHz oscillator), and while enumeration occurs, the USB middleware fails to initialize correctly, resulting in the device being detected as an “Unknown Device.” To enable PLLQ, I tried enabling the USB FS peripheral and then disabling it to avoid pin conflicts with the HS lines, but it didn’t help. Toggling the USB3300 reset pin had no effect. Configuration Details: Initial setup done via CubeMX. USB_OTG_HS configured for ULPI interface. RCC and PLL settings look correct, but PLLQ doesn’t remain enabled. Tried USB Device middleware with CDC class, but initialization fails. Request for Help: Does a constantly high DIR pin mean the PHY is stuck o

We are working with the STM32 Nucleo-G474RE board and using two quadrature encoders—NEMA 23 and NEMA 34—connected through AM26LS32 line receivers to TIM2 and TIM3 respectively, configured in encoder mode. In our project, we initialized TIM2 and TIM3 with `CounterMode_UP`, no prescaler, and appropriate encoder mode settings. We initially tested with pull-down resistors and counter mode set to down, but encountered erratic behavior: encoder counts would overshoot, then suddenly reset to 0 or toggle between 0 and 1. We then tried changing the GPIO configuration to pull-up with counter mode set to up, but received no response from the encoders. Despite using `HAL_TIM_Encoder_Start()` and observing the encoder signals on an oscilloscope (which looked clean), the counter readings remained unstable or stuck. We are using the ITM SWV output to log values via printf. We would appreciate any insights or suggestions from the STM32 community on solving this encoder reading issue, especially in ter

Hi team,            I am working on stm32F7 discovery board, I am working on USB MSC Device however i am not getting , how to configure external flash of this discovery board as Mass Storage. My main goal here is as soon as i connect the controller to PC, the external flash has to detect as mass storage device (predefined size).  regards,Shikamaru  

Hi all, I have a custom board and application using the mentioned MCU, when I use the "run" with the Release option  on STM32CubeIDE and once I use the board alone the FW starts flawless as soon I power up. Now when I use the STM32CumeProgrammer to upload the "Release" bin file the board do not start the FW after powering up the board but need to press reset for it to start. These behavior tells me is not an issues with the NRST's RC circuit. Could anyone help me to solve this issue, cause have a production waiting to solve this issue since all the boards were programmed using the  STM32CumeProgrammer for speed in production and now all of them need to use the reset button to start.Al OB are as suggested in the forums and documentation nBOOT_SEL=1, nBOOT0=1, nBOOT1=1 Thank you in advance.

Hello,I am working with an STM32G431K8T6and using the LL library to configure SPI in master mode.The issue is with the MISO pin (PB4).The pin is configured as SPI input, with no pull-up or pull-down.When PB4 is left unconnected, the voltage is measured at 3.3v.If I short PB4 directly to GND, the current goes up to about 65mA, which looks like the pin is driving strongly,similar to push-pull output.Because of this, the SPI slave cannot pull the line low enough, and communication fails.Configuration Details:void MX_SPI1_Init(void) { /* USER CODE BEGIN SPI1_Init 0 */ /* USER CODE END SPI1_Init 0 */ LL_SPI_InitTypeDef SPI_InitStruct = {0}; LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; /* Peripheral clock enable */ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); /**SPI1 GPIO Configuration PA7 ------> SPI1_MOSI PB3 ------> SPI1_SCK PB4 ------> SPI1_MISO

Hi, I have been trying to implement a logic to flash the updated firmware on top of existing with established DFU mode and using stm32cubeprogrammer. Where I chosen bin file for flashing and I provided the starting address as well. For confirming I have added enough debug prints and from that i never seen the erase function never being called when push the new update through USB.pls see the logsDFU Media registeredUSBD Started1.....6.....GetStatus Add=0x08020000 Cmd=0x016.....GetStatus Add=0x08019000 Cmd=0x016.....GetStatus Add=0x08019000 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x016.....GetStatus Add=0x08019000 Cmd=0x01FLASH_If_Read addr=0x08FFF80C len=46.....GetStatus Add=0x08FFF80C Cmd=0x016.....GetStatus Add=0x08019000 Cmd=0x0

I'm using STM32F429I-DISCO with external SDRAM and DMA2D to render graphics.CPU run at 180 MhzSdram 90mhzLtdc clock: 3mhzLcd : 240*320 color RGB565Issue:I use DMA2D to fill the screen, then on Transfer Complete interrupt, I trigger a second DMA2D to draw a sprite.It works fine in debug mode, but in real-time, the sprite is not drawn.If I switch to polling mode (HAL_DMA2D_PollForTransfer()), it works correctly.The interrupt may fire before SDRAM is truly ready for the next transfer.The question:How to reliably chain DMA2D operations with SDRAM in interrupt mode to fully offload cpu?

Hi,I have a question regarding the backup SRAM in the STM32U5. The reference manual is not clear about this:On the one had, it mentions the following Which seems to indicate that it is possible to place the device in standby without powering SRAM2. HOWEVER, it also says this: This last line (The backup SRAM content is lost in Standby mode without SRAM2 retention. If either RRSB1 or RRSB2 bit is set in Standby mode, the backup SRAM is also retained.) seems to say that it is NOT possible, and one ALWAYS has to retain the 8kB to retain at least the 2kB. What's more, in the PWR_ModesSelection example, the example configurations only include the following 3 options: Which also seem to indicate that it is not possible to only retain the 2kB  So which is it: Is it possible to retain the backup SRAM (2kB) WITHOUT retaining the full 8kB (or the other page) of the SRAM2 bank or not? Thanks for your clarification!Arnout  

Hello,When using stop mode 3 with the stm32u5a9j chip, I noticed a unexpected behaviour when exiting stop mode 3.I have a device connected to the stm32 chip which wakes up the stm32 on rising edge on one of its pin ( GPIOA0 ). This interrupt can be triggered while the stm32u5 is in run mode or in stop mode 3. When the stm32u5 is in run mode and if this interrupt is triggered, only the the EXTI Line0 interrupt is generated by the NVIC as expected.But when the stm32u5 is in stop mode 3, sometimes the NVIC generates 2 interrupts when exiting stop mode 3  the EXTI Line0 interrupt and then the PWR wake-up from Stop 3 interrupt ( both with default priorities, respectively 19 and 85 ) and sometimes ( less often ) only the PWR wake-up from Stop 3 interrupt is generated. It's not clear why the EXTI is generating an interrupt and sometimes it does not when exiting stop mode 3. Is there a way to make sure the EXTI is also generating an interrupt when exiting stop mode 3 o

Hi, I'm using the STM32H753-NUCLEO Board for some SW development, and I'm having some issues with the SPI Handling.I'm attempting to transmit a single 16-bit data packet, however on the scope I'm transmitting two 16-bit data packets. When I change my data packet type to 8 bits, I'm transmitting 4 8-bit data packets.I've scoured the RM0433 manual but cannot find the register which tells the peripheral to only transmit a single data packet.Could someone point me to the correct register and what it should be set to to achieve this please?

HiI created a composite USB device with CDC and UVC classes using usbd. The device is detected, camera image streaming works, and data transfer via CDC (virtual serial port) also works. However, after a random time, communication on the CDC data out endpoint stops. Reopening this endpoint solves the problem. The same thing happens with EP0. When I repeatedly open and close the serial port, EP0 stops receiving data after some time. If I stop video streaming, CDC communication is stable.Sometimes I also get an incorrect video frame when data is transmitted via CDC. I'm using FreeRTOS, but running everything in a single thread didn't solve the problem. I have no further ideas what could be wrong.Any ideas?Artur

I am using two NUCLEO-U385RG-Q boards for I3C communication — one configured as the Controller (Master) and the other as the Target (Slave). I am trying to implement an IBI event with Pending Read Notification, and would like to know whether it is possible to perform Repeated START between the IBI and the subsequent Private Read? The transfer format for Pending Read Notification can be referenced in the following document, specifically Figure 6 – MCTP over I3C packet transfer format: I3C Target to I3C Controller:Management Component Transport Protocol (MCTP) I3C Transport Binding Specification  From the transfer format, it can be seen that Pending Read Notification essentially means that after the Controller receives an IBI event, it then performs a Private Read to the corresponding Target.Between these two operations, either STOP + START or Repeated START can be used. With the current SDK, STOP/START sequence between IBI and Private Read is possible (i.e., the Cont

Hi everyone! I have a working project based on STM32F746 with LCD, Ethernet and SDRAM(IS42S16160J-6TL) and now we are moving it to STM32H753II. I set up a FMC controller and tested whole SDRAM region with 8, 16, and 32 bit access. I use GCC. During this migration I discovered a line of the code that always generate a HardFault error with UNALIGNED flag set. This is this line: if (strncmp(data + i, boundary_str, 9) == 0) from: for (i = 0; i < len; i++) { if (strncmp(data + i, boundary_str, 9) == 0) { boundaryOffset = i + 9; break; } } data is placed in SDRAM like this: char eth_rx_buf[MAX_LENGH] __attribute__((section (".sdram_noncached"))); and boundary_str like this: static const char boundary_str[10] = "boundary="; HardFault happens every time when i becomes 10. MPU settings were copied from STM32F7 project: /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.BaseAddress = 0xC0000000; MPU_I

Hello everyone, I am working with an STM32H753ZI board and I want to set up CAN communication. I’m a bit confused about what changes I need to make. Here are my main questions: Does the STM32H753ZI use the regular CAN peripheral or the newer FDCAN peripheral? In CubeMX, which settings (baud rate, prescaler, seg1, seg2, etc.) are recommended for 500 kbps? Since the H753ZI board doesn’t have an onboard CAN transceiver, which external transceiver IC (e.g., MCP2551, SN65HVD230, TJA1050, etc.) would be best to use with it? Are there any example CubeIDE projects or reference codes specifically for CAN/FDCAN on the STM32H7 series? How to setup the pinout  configuration and clock configuration. I want to make sure I configure the peripheral and wiring correctly before testing. Any guidance, example code, or links to reference materials would be greatly appreciated. Thanks in advance!

  Hello, I am working with an NUCLEO-H753ZI (ADC1/ADC2 with DMA1/DMA2, and ADC3 with BDMA).My goal is to store ADC conversion results directly into a uint32_t buffer using DMA, so that the 16 valid bits from the ADC are automatically zero-extended to 32 bits in memory. The reference manual describes the possible data widths (byte, half-word, word) for peripheral and memory sides, but I could not find a clear statement about what happens when: Peripheral data alignment = half-word (16 bits) Memory data alignment = word (32 bits) Does the STM32H7 DMA (DMA1/DMA2 and BDMA) guarantee that the upper 16 bits are always zeroed when transferring 16-bit peripheral data into 32-bit memory? Or are the upper bits undefined? In CubeMX, when configuring ADC1 or ADC2 with DMA, it is not possible to set MemDataAlignment=WORD in the .ioc file (the tool only allows HALFWORD). Is this a CubeMX limitation, or does it reflect a real hardware restriction? Thanks in advance for

Akkording to AN3155, July 2025: "The highest tested baud rate (BHigh) is 115200." Have tried with 921600 and that seems to work fine.  Is the recommodation from ST that not use above 115200?

HiI modified nBOOT_SEL Bit, but still the PA14-BOOT0 Pin level has no effect. The CPU starts always on in Main flash memory. I have these 2 situations (RM0490 Rev 5 page 53) If PA14 is low level: Main flash starts. This is okIf PA14 has high level: System memory (Internal Bootloader) should start. This is not working. Always application on flash memory starts.This is the Flash_OPTR content: This is the board schematic: J13 is JTAG: this is workingJ12 is access to serial USART loader. RX and TX is connected to PA9/PA10.J12 serial loader is working in case flash is empty. This is the routine for modify the Option Byte: HAL_StatusTypeDef ClearnBootSel() { FLASH_OBProgramInitTypeDef OB; HAL_FLASHEx_OBGetConfig(&OB); /* OB.USERConfig returns the FLASH_OPTR register */ // Use it to check if OB programming is necessary if (OB.USERConfig & FLASH_OPTR_nBOOT_SEL) { HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); OB.OptionType = OPTIONBYTE_USER; OB.USERType = OB_USER_NBOOT_SEL

hi,The PCB with STM32F746zgtx has already been shipped to the customer.Pin PA12 is responsible for controlling the RS485 DIR.The documentation states that Pin PA12 is powered by the Vddusb pin.It turns out that pin PA12 doesn't drive the high voltage (3.3V) because the Vddusb pin isn't connected.I can't make any hardware changes. Is there any way to force this in software?I've tried unsuccessfully:1. Set Open Collector + Pullup,2. Set Push-Pull,3. Set PIN PA11 (which is also powered by Vddusb) as a PULL-UP input, hoping it will transfer to PA12.4. Pin PB14 controls the LED (via ground). This pin also receives a high signal from the Vddusb pin, so I thought it might be possible to transfer the high signal from the LED to pin PA12, but it didn't work.5. I tried setting PA12 as hardware control (RS485).Do you have any ideas?  

The new STM32L4R9 svd file (version 2.0) has renamedTIM1_OR2 to TIM1_AF1,TIM1_OR3 to TIM1_AF2Removed TIM1_OR1 which is in the reference manual containing ETR_ADC1_RMP and TI_RMPAdded a new TIM1_TISEL at offset 0x68 which is not in the current reference manual.Is a new reference manual due and/or are these changes correct?p.s. Thank you for fixing many of my previously reported issues and adding a lot of useful descriptions.Regards, Kc

Hello everyone,I am facing a strange behavior when using ADC scan + DMA with an STM32L476RG.To debug the issue, I created a very simple test code: the MCU performs a scan measurement on 4 channels of ADC1 (PC0, PC1, PC2, and PC3) using DMA.Test setup:ADC1 configured in scan modeDMA transfer to conversions[4] bufferChannels: PC0, PC1, PC2, PC3Observation:On a Nucleo-L476RG (MB1136 C-04), the code works as expected. Each channel returns a value of around ~550 in all positions of conversions[4].On my custom hardware, running the exact same firmware, I see a very different behavior:conversions[0] shows a value around ~2200conversions[1], [2], and [3] remain stuck at 0This issue happens only on my custom board.I have already checked the supply pins:VDD, VDDA, VREF+ → all are properly connected and supplied with ~3.3VGND and VSSA are also properly tiedI will attach the relevant section of my schematic showing the MCU connections.Has anyone faced a similar issue or has suggestions on what cou

I have a small project which should generate an interrupt whenever a DMA transfer has completed. If I build the code for an STM32F411 then it works exactly as expected. If I build that same code for an STM32F401, which is within the same family as the 32F411, then the project is not built correctly. The DMA transfer still happens, but there is no interrupt upon transfer completion.The problem is in the vector table. .word SysTick_Handler .word 0 /* Reserved */ .word EXTI16_PVD_IRQHandler /* EXTI Line 16 interrupt /PVD through EXTI line detection interrupt */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through the EXTI line */ .word EXTI22_RTC_WKUP_IRQHandler /* EXTI Line 22 interrupt /RTC Wakeup interrupt through the EXTI line */ .word FLASH_IRQHandler /* FLASH global interrupt */ .word RCC_IRQHandler /* RCC global interrupt */ .word EXTI0_IRQHandler /* EXTI Line0 interrupt */ .word EXTI1_IRQHandler /* EXTI Line1 interrupt */ .word EX

Hello,I want to use the Timer1 CH1 and CH1N of the STM32H563ZI with dead time generator and break input functionality. It should behave in that way that when the break input (BKIN) is triggered it should goes to a predigined idle state (for CH1 low and for CH1N goes high). After setting the configuration to PWM mode 1 in that way and run the program on oscilloscope I can observe that eg. when the CH1 is low, CH1N is high and the BKIN triggers, the CH1 keep being low, but the CH1N change it state to low for dead time period and again goes high as a predefined idle state. Is it normal behaviour of the timer that even when the output should be high when BKIN occure it is pulling down for dead time and after dead time it is enabling the idle states? 

In STM32G474.svd version 2.1 that can be download from STM32G474RE product page , WWDG peripheral has no interrupt defined but it is actually the first (0th) interrupt. Is this a mistake or there is a reason behind not defining it in the SVD ?

 Dear all,I’m seeing unexpected behavior on an STM32N657. A timer is configured to generate an interrupt every 1 ms, and this works as expected.I would like to use WFI to stop execution and wait for that timer interrupt. I surround the WFI with the usual barriers (DSB before, ISB after). However, when I use WFI, the timer no longer synchronizes and the interrupt is never taken. With WFE, the system resumes correctly, but that is not the functionality I need.The same code works on my other ST targets (M3, M4, M7, M33), and it also works on a non-ST Cortex-M55. I haven’t found anything relevant in the errata.Could you please advise or point me to any known issues or configuration requirements related to WFI on the STM32N657?Many thanks in advance.Kind regards,Edo

HiI have to connect an STM34 Nucleo board to a TMC2209. I have to setup a single wire UART. Only TX is connected with the TMC board.I transmitted a datagram and when I try to receive the response I get back the initial data I have e sent.Does anybody know what could be happening?does anyone has experience controlling a stepper motor with TRINAMIC TMC2209?Please, I need help. I am in a bit of a hurry.Best regards, Raúl