STM32 MCUs Products

Hi ST community, Recently i am working on a project, home automation, and i would like to use STM32F429VIT6 MCU and 3.5 inch 320RGB x 480 LCD display on the project. The LCD display controller is ST7365P from Sitronix, with Frame Memory Size: 320 x 480 x 18-bit = 2,764,800 bits. My question is, is it possible to interface STM32F429VIT6 MCU with the TFT-LCD display through LTDC without using an external RAM just by using the On-chip Frame Memory? Attached are the TFT-LCD display and the ST7365 controller datasheet. Regards,

Hello,we are using a STM32F429.The bootloader is located in the first 64kB. The firmware in the remaining sectors.It erases the remaining sectors of the flash and writes the new firmware.Now, 3.6.5 Read-while-write (RWW) of the reference manual states that "This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank."Does this mean that reads from the same bank as a sector is erased is not allowed?If so, how should the bootloader update the firmware in Bank 0, where the bootloader sits itself?Many thanks in advance for your answer! 

I have a stm32g031k8 board. I was trying to give a pwm input signal like a square wave, measuring the frequency and duty cycle and generate pwm signal of that frequency and duty cycle using another timer. I was also changing the frequency and duty cycle of the input signal on the fly and it should change the output signal instantly. I was unable to do it. I was able to measure the frequency but nothing works. Please help me with the procedure. Thank You.

Hi.I was searching for a crystal that meets the requiremets for the HSE of the MCU I´m using (STM32L4P5RGT6) at the beginning I tried to make the corresponding calcuations by myself but after researching I noticed that for some calculation I needed make physical measurements of the crystal (I dont even have the crystal as well as the oscilloscope) because of that I tried to have some guidance on evalutation boards that implemented the same line of the MCU I was trying to use on its evaluation board, but I found that many of the evaluation board use LSE using 32.768kHz crystals, so in that point I ask my self "What external clock source do I need in first place?" I`m going to implement the above MCU with basic componentes that ones to can start the MCU as well as some DCMI interface ans some serial interfaces as well (I2C, SPI), analog peripherals and USB. I´m beginner in the MCU design so, what external clock source do I need? Thanks for your help. 

Hello,i'm trying to implement firmware upgrade in my Windows application via USART for stm32f103 following AN3155. My issue is with the Write Command. More specifically:- if i send 1 byte of user data at time it works, it's just slow cause i have to introduce 1ms delay or shorter between each write (or it stucks and i get no message from the bootloader)://PSEUDO CODE: for (i=0 to N_byte){ USB_Out_Buffer[0] = FirmwareBytes[current_chunk_num, i]; USB_write(1); //sends 1 byte delayms(1); }- if i send the whole 256 byte block (or lower) it stucks after sending the checksum and i get no message from the bootloader://PSEUDO CODE: for (i=0 to N_byte){ USB_Out_Buffer[i] = FirmwareBytes[current_chunk_num, i]; } USB_write(N_byte+1); //sends 256 bytesI'm using USART on PA9, PA10. i tried everything, reduce baudrate, adding delay etc. Any idea what could be the issue?

We're using a STM32H747IGT6 and using hardware semaphores to coordinate between the two cores.On the CM4 I've set up TIMER3 to run at full blast:  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); LL_TIM_SetPrescaler(TIM3, 0); // Count at system clock LL_TIM_SetAutoReload(TIM3, 0xFFFF); LL_TIM_EnableARRPreload(TIM3); LL_TIM_SetCounterMode(TIM3, LL_TIM_COUNTERMODE_UP); LL_TIM_SetClockDivision(TIM3, LL_TIM_CLOCKDIVISION_DIV1); LL_TIM_EnableCounter(TIM3); I believe that means the timer is running at 240 MHz (do you agree?) which is one tick every 4.166 nsec.So now I grab and release a hardware semaphore that is not used anywhere else in the code:  start_timer = LL_TIM_GetCounter(TIM3); WRITE_REG(HSEM->R[TEST_SEMAPHORE_NUMBER], (HSEM_R_LOCK | LL_HSEM_COREID | SHMEM_CM4_PID)); uint32_t readBack = HSEM->R[TEST_SEMAPHORE_NUMBER]; if (readBack == (HSEM_R_LOCK | LL_HSEM_COREID | SHMEM_CM4_PID)) WRITE_REG(HSEM->R[TEST_SEMAPHORE_NUMBER], (LL_HSEM_COREID |

I have a custom board with an STM32U083KCU6 MCU - see schematics belowVBAT = +3.6VI have 2 boards:1. board: I flashed it via SWD but forgot to enable it in STM32CubeMX, which means that I'm not able to flash it again via SWD2. Board: This time, I remembered to enable SWD inside STM32CubeMX and was able to flash it successfully. It worked fine for a long time, but now it suddenly seems like my ST-LINK V2 programmer is no longer able to flash it for some reason...NRST is connected to RST on the ST-LINK V2 programmer.I can use the same ST-LINK V2 programmer to flash a STM32U083 Nucleo board, so it does not seem like the ST-LINK V2 programmer is brokenSTM32_Programmer_CLI -c port=SWD sn=223215051117303030303032 -d ------------------------------------------------------------------- STM32CubeProgrammer v2.15.0 ------------------------------------------------------------------- libusb: warning [libusb_exit] device 4.76 still referenced libusb: warning [libusb_exit] device 4.75

Application note AN5361 "Setting up with ST-LINK GDB server" says "Set the Cortex®-M7 core running so that the HSEM semaphore is released and Cortex®-M4 wakes up from Stop mode" and this post implies that it's "HSEM 0" which I'm assuming is HSEM channel 0.Am I correct that HSEM channel 0 is not available for use by my application?  Is that fact documented in the Reference Manual (I can't find it anywhere)? 

I am working on a H755zi-Q Nucleo board , I am using the flash memory to store some parameters and i have implemented flash wearing as well, All this works fine , my data persists across resets and is correctly loaded upon reset, and i have even verified this in the memory , in debug mode i see each page being written perfectly on every write command, when i upload a new code or sometimes when i terminate and relaunch the debug session and open memory , i see that data is erased. How do i prevent this?i want to retain that sector's data over flashes and debug sessions, the memory sector i am using is far away from my code's sector, (i am using bank 2 last sector). This is my initial data in the memory, i have entered debug mode, and after performing a new write operation,  here we are again, but from now if i keep performing write operations they are preserved correctly./* * @brief Find the page of the memory sector to write the * data of the params struct */ uin

We try generate signal defined by toggle table , but command do nothink. (except ARR toggles) if (HAL_TIM_OC_Start_DMA(&htim2, TIM_CHANNEL_4, &tim_values[0], idx) != HAL_OK) { Error_Handler(); }have 1.7.0 U5 firmware some known issue ? Or what is required to right setup this.We try add enable GPDMA etc. No change. For ARR is one toggle no based on table. Seems we skip some trigger setup or U5 HAL is buggy .? Pls help. Simply we have table and require toggle for example 20 words table in time.Actual config:main ... /* Initialize all configured peripherals */ MX_GPDMA1_Init(); MX_CRC_Init(); MX_RAMCFG_Init(); MX_DSIHOST_DSI_Init(); MX_LTDC_Init(); MX_TIM3_Init(); MX_USART2_UART_Init(); MX_DCACHE1_Init(); MX_ICACHE_Init(); MX_DMA2D_Init(); MX_GPU2D_Init(); MX_DCACHE2_Init(); MX_TIM2_Init(); MX_TouchGFX_Init(); /* Call PreOsInit function */ static void MX_TIM2_Init(void) { /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTy

In looking at AN3155, USART protocol used in the STM32 bootloader, the following diagram describes the MCU's write protect command sequence from the device side:There is a comment at the bottom which indicates that only certain F and L series chips perform the system reset.  I am working with a STM32U585QI, and I also see that this chip appears to perform a system reset when executing the write protect command.  Is that correct and this comment is just wrong, or am I seeing this unexpectedly?

We are using the STM32L071KZU6 in one of our designs and are facing an issue with bootloader communication over I2C. Specifically, some boards fail to enter the bootloader or respond on the I2C bus, while others function normally. Below are the details of our observations:The MCU is programmed by a CX3 host over I2C.On some boards, the MCU does not respond to the I2C address with an ACK during bootloader flashing.We have monitored BOOT0, nRST, and I2C lines on both working and non-working boards, and the signal waveforms appear identical.In boards where the issue occurs, once the device successfully flashes even once (randomly), it continues to function correctly thereafter with no further flashing issues.We have tried various I2C clock frequencies, ranging from 400 kHz down to 10 kHz, with no consistent improvement.All other electrical and mechanical aspects (including pull-ups on I2C, supply stability, and reset timing) have been reviewed

I'd like to setup the DMA engine to use double buffer mode, but on different size buffers. It seems that there is only one NDTR register per stream, and the user manual says this can only be written to when the stream is disabled.So combining this information, is it the case that both buffer lengths must always be the same size?

Hi, I'm using NuttX as RTOS on my STM32 board. I have a timer set in the DTIMER register, and in the interrupt handler of the SDMMC, if it detects a timeout, the way the code handles it is that does this: 1. disable all transfer related interrupts // flags to the SDMMC mask register. 2. Set "Stop transmission" command to the CPSM command register. 3. Set to the Interrupt clear register the following: STM32_SDMMC_ICR_DATAENDC | // DATAEND flag clear bit STM32_SDMMC_ICR_DCRCFAILC | // DCRCFAIL flag clear bit STM32_SDMMC_ICR_DTIMEOUTC | // DTIMEOUT flag clear bit STM32_SDMMC_ICR_RXOVERRC | // RXOVERR flag clear bit STM32_SDMMC_ICR_TXUNDERRC | // TXUNDERR flag clear bit STM32_SDMMC_ICR_DBCKENDC // DBCKEND flag clear bit However, the problem I'm having is that the IDMA control register remains enabled, and if I try to reset it myself to 0, when I read it back it's still enabled. Before a new I/O is attempted on the sd card, the following registers are (re)set: 1. Set IDMA control regis

Hello,I'm kind of newbie in the STM32 world, I'm more used with another brand of 32bits microcontroller that also have a "parrallel port" for interfacing external ram device.My concern is about the FMC on the STM32H7.I want to read/write a 16bits device.Currently I'm using this configuration (almost the default one) :My code for testing a write operation :.... I can't see any problem in the code but when I check signals with an oscilloscope, I can see that the CPU is issuing 4 consecutive write operation : A0 / A1 are also increasing as if the CPU is writing to 4 different places.How can it be possible.I have seen in the datasheet that when AXI bus and external bus is different size, it can occurs. But in that case how to perform a correct 16 bit operation ??Other people seems to have this kind of trouble but nobody replied with a solution :https://community.st.com/t5/stm32-mcus-products/h7-series-fmc-question/td-p/131535https://community.st.com/t5/stm32-mcus-embedded-softwar

Hello ST Team, We are currently working with the STM32G0B1KCUX series MCU, which has 144 KB RAM and 256 KB Flash.Our objective is to measure the frequency of an incoming signal using TIM1 in Input Capture mode with DMA (Channel 2). Below are the key configuration and issue details: We are interested in capturing frequency using DMA mode without any interrupt callbacks. We need a way to synchronize the transfer completion to ensure the captured data is correct i have Attached timer settings and code snippet Timer Configuration: Timer: TIM1 (16-bit) Clock Frequency: 64 MHz (no prescaler) DMA: Used to capture values without interrupt Slave Mode: Reset mode with trigger on TI1FP1 Input Signal: Frequency Range: 15.8 kHz to 16 kHz Signal Period: Approximately 62.5 µs to 63.3 µs Observation: When checking the DMA_ISR_TCIF2 flag before reading, the time between frequency measurements varies inconsistently — sometimes 1ms, 2ms, or 3ms. However, if we remove the DMA com

Hello,STM32F411CE microcontroller.Where can I find, which of command the Erase or Extended Erase command is supported by the UART bootloader?There is a note 4 in the AN3155 (page 7 and,also see Figure 1 below) which says that the Erase (x043) and Extended Erase (0x44) are exclusive. A device can support either the Erase command or the Extended Erase command, but not both.    Figure 1: 

I am trying to run the Secure Boot examples from STM32CubeL5 and have everything built, but on step 2 where I run `TFM_SBSFU_Boot\STM32CubeIDE\regression.sh` I am having an error where I cannot program the option bytes.(Another similar thread was with someone who bought a counterfeit part so I'll also mention that I bought the kit from ST.)This is the script output $ ./regression.sh regression script started Regression to RDP 0, enable tz ------------------------------------------------------------------- STM32CubeProgrammer v2.19.0 ------------------------------------------------------------------- ST-LINK SN : 004600313137510B33333639 ST-LINK FW : V3J13M4 Board : STM32L562E-DK Voltage : 3.29V SWD freq : 8000 KHz Connect mode: Hot Plug Reset mode : Software reset Device ID : 0x472 Revision ID : Rev Z Device name : STM32L5xx Flash size : 512 KBytes (default) Device type : MCU Device CPU : Cortex-M33 BL Version : -- UPLOADING OPTION BYTES DATA ... Bank : 0x00 Address : 0

Hey everyone,I'm working on a custom board based on the STM32H753 MCU. I successfully programmed it using STM32CubeIDE initially, but ran into an issue when trying to re-flash it — I got the error:"Unable to erase flash memory to reprogram it"To work around this, I connected to the board using STM32CubeProgrammer and performed a full chip erase using the following settings (details below). I clicked Apply, and the flash erase appeared successful. After erasing, I’m no longer able to connect to the board via either Cube IDE or Cube Programmer. I now get:"Unable to get the core ID" Debug Interface: ST-Link  externalBoard was connecting and programming before the flash eraseNow completely unresponsive via SWD.Does full flash erase wipe the area that contains the boot/configuration code, preventing debug access?What hardware signals should I verify?Is there a way to force the MCU into a recoverable modeI will also share the schematics Note:This is not exactly the same a

Here in the below image from the Cube MX it suggests that, SET all the free pins as analog (to optimize the power consumption). How does it help. Also is it applicable to all the controller families?  

Hi, I have a question about this highlighted text in the AN2867 document refering to the "calculating external resistor" paragraph As I understood the condition to use a Rexternal is "if the power disipated in the crystal is higher than the value specified by the crystal manufacturer", as shown above so my question is how to check the power dissipated in the crystal? how to know if I`ll need to use Rext before have a physical implementation of my MCU thanks for your helpOne more extra question (not a technical one) is it normal to feel a little bit overwelmed some times doings this kind of desing? (is my first time designig the STM32 MCU lets say from scratch)  Thanks!

I have been trying to figure out why I keep getting consistent hard faults when trying to access peripheral instances after waking from Stop Mode 2.  Here is the code I am usingFor entering stop mode:static void SystemClockConfig_STOP(void) { /* A) Ensure V_CORE supports 120 MHz again */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); /* B) FLASH: raise latency before any SYSCLK jump */ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_5); while (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_5) {} /* C) Handle AHB overshoot if needed */ if ((RCC->CFGR & RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); } /* D) Bring HSE & PLL back */ __HAL_RCC_HSE_CONFIG(RCC_HSE_ON); while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY)) {} __HAL_RCC_PLL_ENABLE(); while (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)) {} /* E) Switch to PLL */ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK); while ((__HAL_RCC_GET_SYSCLK_

Dear ST Support Team,I am currently working on a USB Host Mass Storage Class (MSC) implementation using the STM32H750VBT6 microcontroller.:white_heavy_check_mark: The configuration is done using STM32CubeMX (version: [ V6.14.1]):white_heavy_check_mark: Firmware package used: STM32Cube FW_H7 V1.12.1:white_heavy_check_mark: USB_OTG_FS is configured in Host Only mode, and FATFS is integrated via USB Host interface.:white_heavy_check_mark: USB 2.0 flash drives are detected and work as expected.:cross_mark: However, when I connect USB 3.0 / 3.1 / 3.2 flash drives (FAT32 formatted), the drives are **not detected**, and `Appli_state` remains `APPLICATION_IDLE`.---:magnifying_glass_tilted_left: I would like clarification on:1. Whether the STM32H750VBT6 supports USB 3.x devices (backward compatibility) in USB Host mode?2. If not supported, is there any workaround to support USB 3.0+ flash drives with this MCU?3. Is there any documented limitation or Error regarding USB 3.x detection failure?4.

I was comparing the STM32 Debug Support documentation (Chapter 26 in RM0360) with official ARM documentation and noticed something that I cannot explain. The documentation for the SW-AP registers appears to be wrong. It is simply a rewording of the documentation of the SW-DP registers. The IHI0031 document from ARM shows the correct definitions of the SW-AP registers. It however leaves certain fields as implementation defined and I believe this information should be in RM0360. I have checked and the same appears in the RMs for the G030 and the C030. I am interested in knowing, for example, the details of the PROT bit field (Bits 30..24) in the CSW register which should be at address 0x00 in the AP.  

 Hello everyone,I have been working with the STM32L431RCTx on a project where I need to log audio data to an SD card. I have attempted to do multiple things unsuccessfully and would really appreciate your help to see where I am going wrong. I am new to working with SD cards, so I recognise that I may have missed something in my research. For all of the below, I have tested with SDHC and SDXC cards with the same results.First; I have tried to setup the SDMMC interface with at least 20MHz clock speed (clock divide factor 0)The behaviour is very intermittent. It sometimes mounts, opens, writes, closes, then unmounts, but other times will not open or write without an FR_DISK_ERR. My error handling attempts to correct any errors, but I believe there is no fix for a FR_DISK_ERR right? After a while a Hard Fault occurs.I tried again with 40MHz clock speed and clock divide factor of 4. With these settings it goes for longer without errors, however now and then there are still errors that