STM32 MCUs Products

Hi There,I have setup TIMER4 on STM32G484 device for overflow event and enabled interrupt for events. Everything works fine and as expected with correct fire time if I RESET the CNT register in the ISR. However, if I do not, it seems to do some level of free-running.I only inquire about this, as in all of the STM32 reference manual images, when an overflow event occurs and it's been enabled to detect this, the CNT resets in the peripheral (as long as not single shot mode). So I'm just wanting to confirm that this seems normal and is not a hint that I've misconfigured something. Here are my configuration calls and ISR, I verify the ISR timing on the scope with a GPIO toggling (not shown here).    Register_t rcc_tim4_en = { .address = 0x40021058, .mask = 0x1, .bit_pos = 2 }; Read_Then_Write_Masked(rcc_tim4_en, 0x1); Register_t tim4_cr_dir = { .address = k_tim4_addr + k_

Hi,When HAL_Uart_errorhandler is triggered, how can we check if the trigger is for reception or transmission?

Hi I am using STM32F407 DISCOVERY BOARD and I am able to make the board change to boot mode using a another controller.After boot mode change over I need to program the memory of STM32F407 DISCOVERY BOARD by UART communication.Here I am unable to get the ack when I provide the sync command(0x7f).But when I completely remove the power and provide the power back The 0x7f is acknowledged with 0x79. In real time application I cannot reset the power manually.Am i missing anything ...? Please share your insights on this.  

I am currently using stm32f407 with FreeRTOS as operating system in MDK IDE. Recently, When I added a new function ( The new function is ospf routing algorithm, and it is very complex and involves many files ) to my project, I began to encounter hard fought exception. I use the call stack window to check the context of the exception and found that the context is uart_send function. Since I redirect the printf function to uart_send and use it to print debug information so uart_send is called most frequently. When I comment the new added ospf function, everything goes fine, no hard fault exception and uart_send goes fine. So, the hard fault exception comes from the new added ospf function. However, I have no idea which part of the ospf function goes wrong and the call stack window gave nothing useful. I have no idea what to do next? Could anyone tell me what to do next? Is there a procedure to debug a hard falt exception? Thanks in advance!

This is mostly a post to help people who try to google this later since I couldn't find anything. If you look at AN2606 table 197, it lists the minimum startup time for the bootloader on a bunch of different STM32 microcontrollers. For some reason, just two MCUs have "NA" listed including the chip I'm currently working with - the STM32L4R. So if anyone is wondering, my testing has shown that it takes ~90ms from reset/powerup to when the chip will ACK the 0x7F message on USART.I am curious though, does anyone know why no time is listed for these chips?

Recently, I have been working on a project that intends to utilize the v9.x bootloader on an STM32L471VGT6 through the SPI 2 port. When utilizing the write memory command, I would find that the STM32L4 would occasionally have 0xFFFFFFFFFFFFFFFF written to its flash rather than the data I had requested. The frequency of this error increased the higher the baud rate of the SPI was and I found the issue was also much more prevalent in polling mode vs DMA mode. I happened to be reading through AN2606 and found in the version history for the L496 that theres is a known limitation on that processor with SPI writes. The behaviour listed was identical to what I was observing on the L4 and thankfully, the listed WA1 also solved the issue for the L4. Thus, I believe that the SPI write failure described for the L496 bootloader also exists on the L47 family and is currently undocumented. 

Hello,I am currently working on sensorless PI control for a BLDC motor, and I am using the STM32F303ZE MCU for this project.In sensorless BLDC motor control, the motor must transition to the next commutation step 30 electrical degrees after the zero-crossing point (ZCP) of the unenergized phase’s Back EMF (BEMF). Therefore, I need to continuously monitor the BEMF of each phase using the ADC.For my BLDC motor control strategy, I am implementing a unipolar PWM modulation technique. During the ON period of PWM, I need to sample the BEMF voltage, DC bus voltage, and DC bus current. Specifically, I want the ADC conversion to occur at around 90% of the ON duration of the PWM cycle.However, since the duty cycle of the PWM is constantly changing due to the PI controller, the ADC must always trigger at the dynamically changing 90% point of the ON period.My questions:How can I configure the STM32F303ZE to trigger the ADC conversion at 90% of the ON dur

I am working on a STM32H723 microcontroller and I am trying to use and SPI communication in mixed mode, i.e. normal and DMA.The reason I need this is because I have a third party software stack for a device that is set up in a certain way, and it cyclically has to send small packets before sendind a big packet of user data. The application requires hard real-timeness so I want this exchange to be as fast and as little CPU blocking as possible. Considering these transfers must follow a certain order and that the stack I'm using is not organised as a state machine, I can only send the little packets in blocking mode, but then I'd like to send the big packet in DMA mode. The problem I'm encountering is that after using once the SPI transfer in DMA mode, the blocking transfers don't work anymore. When debugging I see that the periphery becomes permanently busy when trying to perform a normal transfer after using it in DMA mode in the previous cycle. I

Hi,I am using STM32N6570-DK kit. In my application I need ~3.5MB of RAM but if I allocate more than 256KB of RAM I get the error "region `RAM' overflowed by xxxx bytes".  I got the same results as well when I imported "UART_HyperTerminal_IT" example for STM32N6 and added 256KB buffer. I got the same error "region `RAM' overflowed by 3328 bytes". I am attaching the same code here for reference.I thought STM32N6 has 4.2MB of RAM as mentioned in datasheet. How can I fully utilize it? 

 I am working on a prototype board using the STM32H725VGT, based on an existing custom board where LWIP/RTOS Ethernet is already working. Since I have a preference to keep the same MCU for the next design, I am evaluating its ability to support an 8-bit wide data bus with a strobe clock and DMA write-only transfers. I have a few specific questions:1. OctoSPI Availability:• In STM32CubeIDE, the OctoSPI peripheral is disabled for this MCU/package.• I could not find a clear reason in the datasheet or reference manual. Why is it unavailable, and is there any way to enable it?

Im building some phase shifting control sensing for a Dual Active Bridge.Im using TIMA and TIMD (shown in pictures) in retrigerable single mode, both signals are triggered by sepparate CR from the master timer. https://community.st.com/t5/stm32-mcus-products/synching-hrtim-s-tima-and-timb/td-p/770972Im trying to trigger ADC measurements only on the high side of the PWM but im getting low side aswel.

Hi,I am encountering a hard fault on my STM32F407ZG when using snprintf(). We are using FreeRTOS for the development.The system resets due to a precise data access violation (PRECISERR).Below is the fault status: HFSR: 0x40000000 BFAR: 0x38383600 BF: 0x82 PC: 0x0806D62E at "_Balloc"  This error occurs randomly after multiple calls to snprintf(). Below is a simplified version of my actual code: #define BUF_SIZE 10 char temp_str[9][BUF_SIZE]; float temp[9]; for (int n = 0; n < 9; n++) { snprintf(temp_str[n], BUF_SIZE, "%.3g", temp[n]); } Fault Trace: task1() → snprintf() → _svfprintf_r() → _dtoa_r() → _Balloc() → <sign

Greetings!I have a board with STM32H747XI and SN65DSI84-Q1 as a converter from DSI to LVDS.The issue is that I can not get video output from MCU to 2ch LVDS panel 1920x720 with any configuration I'm trying. The main issue is that I'm getting HAL_DSI_ERROR_OVF error code on DSI side, and no any LTDC interrupts. It behaves the same regardless LTDC/DSI clocks.When I init DSI and configure SN65DSI84 through I2C and enable Test Pattern generation (register 0x3C) I can see it, so DSI clock and the converter itself works.Another issue is that when test pattern generation on converter side is disabled, on most configurations I'm getting CHA_SYNCH_ERR error read through I2C: When the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet.Also, I tried to enable test pattern gen

Posted on March 11, 2018 at 23:41Hi !I'm excited to join the ST community! I hope someone can solve my problem.I am experiencing timing issues when converting an ADC.Here is the configuration of my project:- The timer 3 is configured in center aligned mode, Trigger output ENABLE on update events, PWM signal generation- ADC: Scan conversion mode enabled, DMA in continuous request ENABLE, NB of conversion: 4, EOC: flag at the end of all conversion. External trigger source Timer 3 out event on rising edge.What I want to do: I want to start the conversion of 4 channels(scan conversion) when the timer 3 is in the middle of the PWM pulse.My problem: Actually my conversion seems well started on rising edge but also on falling edge. I join screenshots of the oscilloscope illustrating

When using DMA to do a SPI transmit, I found a strange behavior. The problem is, that the communication to the DAC works for a few seconds, depending on the used frequency. After the few seconds only 1 byte instead of 3 bytes are sent and the NSS Pin (Hardware regulated) stays low. You can even see these two data items to transfer in S1NDTR (NDT). I used the approximately same code with Software NSS without any problem.I also get a DMA FIFO Error (FEIF) directly after starting the DMA stream, even when using DMA circular mode. Not every time but over 50% of the times when the communication is working I get the FEIF. When the communication is not working anymore, I do not get the FEIF anymore. I found these factors influencing the error:- Using DMA normal mode/ circular mode -> no difference- Enabling DMA FIFO -> no difference- Increase frequency of sending values to the DAC: communication breaks very fast- Decrease frequenc

Posted on May 19, 2017 at 01:02Issue:USB Core issing interrupt at a rate of 8.65us causing high CPU loading.Software/Chip:Using USB Host/CDC from STM32Cube V1.15 on a STM32F429 board.   USB interrupt sources:- SOF Interrupts (It is not needed for CDC type transfers) turned this interrupt off and still getting high interrupt rate.   This is configured inHAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg).....  /* Enable interrupts matching to the Host mode ONLY */   USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\                     USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\    &nb

I noticed that for STM32L010F4 in stop mode (“HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);”) the power consumption is around 330µA when the STLINK is connected to the MCU. When I disconnected the STLINK debugger wires, the power consumption dropped to the expected 0.6µA. Interestingly, the high power consumption happens even when the STLINK itself is disconnected from my computer (its USB cable unplugged), as long as it’s still connected to the MCU. Is this expected?Thanks!

Given an MCU (say an STM32H755ZIT) and a function (say SPI2_MOSI), how can you find which pins may be configured as SPI2_MOSI, short of clicking on every pin in the Pinout View of the MX Device Configuration Tools?

I'm using the STM32H753ZIT6 NUCLEO Board. For some reason the User LED's are on by default even without any code on it. I tried to press the reset button but it would just blink the led's. I read on another forum to short the BOOT0 and Vdd pins but was hesitant to try that. The board works fine sometimes but it tends to give random/no outputs some times. 

Hello,I would like to configure PA11 as an EXTI pin. I know that there exists the hardware limitation that there cannot exist two pins with the same pin number in different ports configured as an EXTI pin (I.E., I could not configure both PB11 and PA11 as EXTI inputs). PB11 is already configured as a UART RX pin. Will there be any conflict if I now attempt to configure PA11 as an EXTI input pin, I.E. a low bit being received by PB11 triggers the EXTI interrupt on pin 11? Or does this conflict only occur when two pins of the same number are both configured as EXTI inputs? 

We are on the second generation of prototype here. On the first generation I had an MCU fail for reasons I couldn't trace.  This was from a set of six. I have now powered seven of the second generation two have had MCU failures.  The second failure was on the prototype's initial turn on.  No code had been loaded into it.  A hole blew out of the part when power was applied. All failed parts then shunted the VCC to ground with a low impedance, less than 100 ohms. I have included part of our schematic.  Do you see anything that could explain this failure?   Best regards, Bill Grimm - Zdiode

Good day Folks,I am hoping you are able to shed some light on this odd XSPI clock behaviour.  I have connected XSPI2 to a W25Q64 Flash in QSPI mode.There are 'preamble' clocks present prior to the NCS being asserted. I've noticed that the number of preamble clocks depends on the frequency of the bus. The least I have seen is 150 clocks. As you can see below it's 641 clocks, prior to the NCS falling.I am guessing the clock is used internal by the XSPI peripheral, however the 'noise' on the bus certainly is undesirable.This prevents me from using a NCS other than the dedicated NCS pin. Other than that it looks like it cr

I want to create and application on a STM32H745XI-DISCO. I am not using M7 core only M4.Reference manual says that upto 864kB of SRAM  and 2MB of flash are available.I will receive the application sw via Can. My bootloader will save it RAM and after checking CRC etc., It will write this to internal flash. App code is around 300 kB. So 256kB of flash and 512 kB of RAM would be sufficient. After writing to flash sw will jump to application.The application sw will receive data which is arund 730kB via can and it will save it to flash.Here is a part of ST generated linker for bootloader;   /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x10048000; /* previously = 0x10048000, end of RAM */ /* Generate a link error if heap and stack don't fit into RAM */ _Min_Heap_Size = 0x200; /* previously = 0x200, required amount of heap */ _M

Good afternoon,  I have some questions for reading multiple channels of the ADC in continuous mode and map the results in the DMA. I have been able to monitor the voltage coming from a potentiometer and map it into the DMA and i can see the values in the "Live expression window". For doing so i have had to creater an ADCQueue and an ADCNode for the channel I am monitoring.  Now, the problem arises when i try to monitor multiple channels. Do i have to create as many Queues and Nodes as channels i have? Do i have to create as many buffers as channels i have and therefore all the links?  Find attached the part of the code where I declare the buffers: /* USER CODE BEGIN 0 */ #define ADC_CONVERTED_DATA_BUFFER_SIZE ((uint32_t) 32) uint32_t aADCxConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; uint32_t secondVariable[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* USER CODE END 0 */ MX_ADCQueu

Hello everyone  New STM32 user here, more specifically STM32 U545 RE-Q. I am kind of new and i would like to start acquiring some data with the STM32 ADC, triggered by a timer, and send the data to the DMA so that i can use the CPU for other stuff. Do you guys have any projects that involve this functionality? Any recomendations on where/how to start?  I am aware that i can use some other projects and theres one for the U575 that involves the ADC with the DMA.However, i have not been able to configure it for my nucleo successfully ... Any advice will be welcomed ... Thank you  Marc