Question
Not getting interrupt on PC13 pin stm32h723zgt6 user button
- August 2, 2025
- 3 replies
- 431 views
NUCLEO-H723ZG (MB1364)
Please verify the code and check ?
/*
* 001led_toggle.c
*
* Created on: Jul 31, 2025
* Author: relfo
*/
#include<string.h>
#include "stm32h7xx.h"
#include "stm32h7xx_gpio_driver.h"
void delay(void)
{
for(uint32_t i=0;i<500000;i++);
}
int main(void)
{
GPIO_Handle_t gpioled,ledbutton;
memset(&gpioled,0,sizeof(gpioled));
memset(&ledbutton,0,sizeof(ledbutton));
gpioled.pGPIOx=GPIOB;
gpioled.GPIO_PinConfig.GPIO_PinNumber= GPIO_PIN_NO_14;
gpioled.GPIO_PinConfig.GPIO_PinMode=GPIO_MODE_OUTPUT;
gpioled.GPIO_PinConfig.GPIO_PinSpeed=GPIO_SPEED_FAST;
gpioled.GPIO_PinConfig.GPIO_PinOPType=GPIO_OP_TYPE_PP;
gpioled.GPIO_PinConfig.GPIO_PinPuPd_control=GPIO_NO_PUPD;
ledbutton.pGPIOx=GPIOC;
ledbutton.GPIO_PinConfig.GPIO_PinNumber= GPIO_PIN_NO_13;
ledbutton.GPIO_PinConfig.GPIO_PinMode=GPIO_MODE_IT_RT;
ledbutton.GPIO_PinConfig.GPIO_PinSpeed=GPIO_SPEED_FAST;
ledbutton.GPIO_PinConfig.GPIO_PinPuPd_control=GPIO_NO_PUPD;
GPIO_Periclockcontrol(GPIOB, ENABLE);
GPIO_Periclockcontrol(GPIOC, ENABLE);
GPIO_Init(&gpioled);
GPIO_Init(&ledbutton);
GPIO_WriteToOutputPin(GPIOB,GPIO_PIN_NO_14,GPIO_PIN_RESET);
GPIO_IRQPriorityConfig(IRQ_NO_EXTI15_10,5);
GPIO_IRQInterruptConfig(IRQ_NO_EXTI15_10,ENABLE);
while(1);
}
void EXTI15_10_IRQHandler(void)
{
// delay();
GPIO_IRQHandling(GPIO_PIN_NO_13);
GPIO_ToggleOutputPin(GPIOB, GPIO_PIN_NO_14);
}/*
* stm32h7xx.h
*
* Created on: Jul 20, 2025
* Author: relfo
*/
#include <stdint.h>
#ifndef INC_STM32H7XX_H_
#define INC_STM32H7XX_H_
#define __vo volatile
/**********************************START:Processor Specific Details **********************************/
/*
* ARM Cortex Mx Processor NVIC ISERx register Addresses
*/
#define NVIC_ISER0 ( (__vo uint32_t*)0xE000E100 )
#define NVIC_ISER1 ( (__vo uint32_t*)0xE000E104 )
#define NVIC_ISER2 ( (__vo uint32_t*)0xE000E108 )
#define NVIC_ISER3 ( (__vo uint32_t*)0xE000E10C )
/*
* ARM Cortex Mx Processor NVIC ICERx register Addresses
*/
#define NVIC_ICER0 ((__vo uint32_t*)0XE000E180)
#define NVIC_ICER1 ((__vo uint32_t*)0XE000E184)
#define NVIC_ICER2 ((__vo uint32_t*)0XE000E188)
#define NVIC_ICER3 ((__vo uint32_t*)0XE000E18C)
/*
* ARM Cortex Mx Processor Priority Register Address Calculation
*/
#define NVIC_PR_BASE_ADDR ((__vo uint32_t*)0xE000E400)
/*
* ARM Cortex Mx Processor number of priority bits implemented in Priority Register
*/
#define NO_PR_BITS_IMPLEMENTED 4
/*
* base addresses of FLASH and SRAM
*/
#define FLASH_BASEADDR 0x08000000U // FLASH MEMORY BASE ADDRESS
#define SRAM1_BASEADDR 0x30000000U
#define SRAM2_BASEADDR 0x30004000U
#define ROM_BASEADDR 0x1FF00000U //SYSTEM MEMORY
#define SRAM SRAM1_BASEADDR
/*
* AHBx and APBx Bus Peripheral base address
*/
#define PERIPH_BASE 0x40000000U
#define APB1PERIPH_BASE 0x40000000U
#define APB2PERIPH_BASE 0x40010000U
#define APB3PERIPH_BASE 0x50000000U
#define APB4PERIPH_BASE 0x58000000U
#define AHB1PERIPH_BASE 0x40020000U
#define AHB2PERIPH_BASE 0x48020000U
#define AHB3PERIPH_BASE 0x51000000U
#define AHB4PERIPH_BASE 0x58020000U
/*
* BASE ADDRESS OF PERIPHERAL HANGING ON THE AHB4 BUS
*/
#define GPIOA_BASEADDR (AHB4PERIPH_BASE + 0x0000)
#define GPIOB_BASEADDR (AHB4PERIPH_BASE + 0x0400)
#define GPIOC_BASEADDR (AHB4PERIPH_BASE + 0x0800)
#define GPIOD_BASEADDR (AHB4PERIPH_BASE + 0x0C00)
#define GPIOE_BASEADDR (AHB4PERIPH_BASE + 0x1000)
#define GPIOF_BASEADDR (AHB4PERIPH_BASE + 0x1400)
#define GPIOG_BASEADDR (AHB4PERIPH_BASE + 0x1800)
#define GPIOH_BASEADDR (AHB4PERIPH_BASE + 0x1C00)
#define GPIOJ_BASEADDR (AHB4PERIPH_BASE + 0x2400)
#define GPIOK_BASEADDR (AHB4PERIPH_BASE + 0x2800)
#define RCC_BASEADDR (AHB4PERIPH_BASE + 0x4400)
/*
* BASE ADDRESS OF THE PERIPHERAL HANGING ON APB1 BUS
*/
#define I2C1_BASEADDR (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASEADDR (APB1PERIPH_BASE + 0x5800)
#define I2C3_BASEADDR (APB1PERIPH_BASE + 0x5C00)
#define I2C5_BASEADDR (APB1PERIPH_BASE + 0x6400)
#define SPI2_BASEADDR (APB1PERIPH_BASE + 0x3800)
#define USART2_BASEADDR (APB1PERIPH_BASE + 0x4400)
#define UART4_BASEADDR (APB1PERIPH_BASE + 0x4C00)
/*
* BASE ADDRESS OF THE PERIPHERAL HANGING ON APB2BUS
*/
/*
* BASE ADDRESS OF THE PERIPHERAL HANGING ON APB3 BUS
*/
/*
* BASE ADDRESS OF THE PERIPHERAL HANGING ON APB4 BUS
*/
#define EXTI_BASEADDR (APB4PERIPH_BASE + 0x0000)
#define SYSCFG_BASEADDR (APB4PERIPH_BASE + 0x0400)
/*******************************PERIPERAL REGISTER DEFINATION STRUCTURE FOR GPIO *****************/
typedef struct
{
__vo uint32_t MODER; // GPIO port mode register ADDRESS OFFSET 0x0000
__vo uint32_t OTYPER; // GPIO port output type register
__vo uint32_t OSPEEDR; // GPIO port output speed register
__vo uint32_t PUPDR; // GPIO port pull-up/pull-down register
__vo uint32_t IDR;
__vo uint32_t ODR;
__vo uint32_t BSRR;
__vo uint32_t LCKR;
__vo uint32_t AFR[2];
}GPIO_RegDef_t;
/*
* *****************************RCC REGISTER DEFINATION STRUCTURE*******************************
*/
typedef struct
{
__vo uint32_t CR; //address offset 0x000
__vo uint32_t HSICFGR; //address offset 0x004
__vo uint32_t CRRCR; //address offset 0x008
__vo uint32_t CSICFGR; //address offset 0x00C
__vo uint32_t CFGR; //address offset 0x010
uint32_t reserved1; //address offset 0x014
__vo uint32_t D1CFGR; //address offset 0x018
__vo uint32_t D2CFGR; //address offset 0x01C
__vo uint32_t D3CFGR; //address offset 0x020
uint32_t reserved2; //address offset 0x024
__vo uint32_t PLLCKSELR; //address offset 0x028
__vo uint32_t PLLCFGR; //address offset 0x02C
__vo uint32_t PLL1DIVR; //address offset 0x030
__vo uint32_t PLL1FRACR; //address offset 0x034
__vo uint32_t PLL2DIVR; //address offset 0x038
__vo uint32_t PLL2FRACR; //address offset 0x03C
__vo uint32_t PLL3DIVR; //address offset 0x040
__vo uint32_t PLL3FRACR; //address offset 0x044
uint32_t reserved3; //address offset 0x048
__vo uint32_t D1CCIPR; //address offset 0x04C
__vo uint32_t D2CCIP1R; //address offset 0x050
__vo uint32_t D2CCIP2R; //address offset 0x054
__vo uint32_t D3CCIPR; //address offset 0x058
uint32_t reserved4; //address offset 0x05C
__vo uint32_t CIER; //address offset 0x060
__vo uint32_t CIFR; //address offset 0x064
__vo uint32_t CICR; //address offset 0x068
uint32_t reserved5; //address offset 0x06C
__vo uint32_t BDCR; //address offset 0x070
__vo uint32_t CSR; //address offset 0x074
uint32_t reserved6; //address offset 0x078
__vo uint32_t AHB3RSTR; //address offset 0x07C
__vo uint32_t AHB1RSTR; //address offset 0x080
__vo uint32_t AHB2RSTR; //address offset 0x084
__vo uint32_t AHB4RSTR; //address offset 0x088
__vo uint32_t APB3RSTR; //address offset 0x08C
__vo uint32_t APB1LRSTR; //address offset 0x090
__vo uint32_t APB1HRSTR; //address offset 0x094
__vo uint32_t APB2RSTR; //address offset 0x098
__vo uint32_t APB4RSTR; //address offset 0x09C
__vo uint32_t GCR; //address offset 0x0A0
uint32_t reserved7; //address offset 0x0A4
__vo uint32_t D3AMR; //address offset 0x0A8
uint32_t reserved8[9];//address offset0x0AC-0x0CC
__vo uint32_t RSR; //address offset 0x0D0
__vo uint32_t AHB3ENR; //address offset 0x0D4
__vo uint32_t AHB1ENR; //address offset 0x0D8
__vo uint32_t AHB2ENR; //address offset 0x0DC
__vo uint32_t AHB4ENR; //address offset 0x0E0
__vo uint32_t APB3ENR; //address offset 0x0E4
__vo uint32_t APB1LENR; //address offset 0x0E8
__vo uint32_t APB1HENR; //address offset 0x0EC
__vo uint32_t APB2ENR; //address offset 0x0F0
__vo uint32_t APB4ENR; //address offset 0x0F4
uint32_t reserved9; //address offset 0x0F8
__vo uint32_t AHB3LPENR; //address offset 0x0FC
__vo uint32_t AHB1LPENR; //address offset 0x100
__vo uint32_t AHB2LPENR; //address offset 0x104
__vo uint32_t AHB4LPENR; //address offset 0x108
__vo uint32_t APB3LPENR; //address offset 0x10C
__vo uint32_t APB1LLPENR; //address offset 0x110
__vo uint32_t APB1HLPENR; //address offset 0x114
__vo uint32_t APB2LPENR; //address offset 0x118
__vo uint32_t APB4LPENR; //address offset 0x11C
uint32_t reserved10[4]; //address offset 0x120-0x12C
__vo uint32_t C1_RSR; //address offset 0x130
__vo uint32_t C1_AHB3ENR; //address offset 0x134
__vo uint32_t C1_AHB1ENR; //address offset 0x138
__vo uint32_t C1_AHB2ENR; //address offset 0x13C
__vo uint32_t C1_AHB4ENR; //address offset 0x140
__vo uint32_t C1_APB3ENR; //address offset 0x144
__vo uint32_t C1_APB1LENR;//address offset 0x148
__vo uint32_t C1_APB1HENR;//address offset 0x14C
__vo uint32_t C1_APB2ENR; //address offset 0x150
__vo uint32_t C1_APB4ENR; //address offset 0x154
uint32_t reserved11; //address offset 0x158
__vo uint32_t C1_AHB3LPENR;//address offset 0x15C
__vo uint32_t C1_AHB1LPENR;//address offset 0x160
__vo uint32_t C1_AHB2LPENR;//address offset 0x164
__vo uint32_t C1_AHB4LPENR;//address offset 0x168
__vo uint32_t C1_APB3LPENR;//address offset 0x16C
__vo uint32_t C1_APB1LLPENR;//address offset 0x170
__vo uint32_t C1_APB1HLPENR;//address offset 0x174
__vo uint32_t C1_APB2LPENR;//address offset 0x178
__vo uint32_t C1_APB4LPENR;//address offset 0x17C
uint32_t reserved12[32];//address offset 0x180-0x1FC
}RCC_RegDef_t;
/*******************************PERIPERAL REGISTER DEFINATION STRUCTURE FOR EXTI *****************/
typedef struct
{
__vo uint32_t RTSR1; //address offset 0x00
__vo uint32_t FTSR1; //address offset 0x04
__vo uint32_t SWIER1; //address offset 0x08
__vo uint32_t D3PMR1; //address offset 0x0C
__vo uint32_t D3PCR1L; //address offset 0x10
__vo uint32_t D3PCR1H; //address offset 0x14
__vo uint32_t RTSR2; //address offset 0x20
__vo uint32_t FTSR2; //address offset 0x24
__vo uint32_t SWIER2; //address offset 0x28
__vo uint32_t D3PMR2; //address offset 0x2C
__vo uint32_t D3PCR2L; //address offset 0x30
__vo uint32_t D3PCR2H; //address offset 0x34
__vo uint32_t RTSR3; //address offset 0x40
__vo uint32_t FTSR3; //address offset 0x44
__vo uint32_t SWIER3; //address offset 0x48
__vo uint32_t D3PMR3; //address offset 0x4C
__vo uint32_t D3PCR3L; //address offset 0x50
__vo uint32_t D3PCR3H; //address offset 0x54
uint32_t reserved1[10]; //address offset 0x58-0x7C
__vo uint32_t CPUIMR1; //address offset 0x80
__vo uint32_t CPUEMR1; //address offset 0x84
__vo uint32_t CPUPR1; //address offset 0x88
__vo uint32_t CPUIMR2; //address offset 0x90
__vo uint32_t CPUEMR2; //address offset 0x94
__vo uint32_t CPUPR2; //address offset 0x98
__vo uint32_t CPUIMR3; //address offset 0xA0
__vo uint32_t CPUEMR3; //address offset 0xA4
__vo uint32_t CPUPR3; //address offset 0xA8
uint32_t reserved2[5]; //address offset 0xAC-0xBC
}EXTI_RegDef_t;
/*******************************PERIPERAL REGISTER DEFINATION STRUCTURE FOR SYSCFG *****************/
typedef struct
{
__vo uint32_t reserved1; //address offset 0x00
__vo uint32_t PMCR; //address offset 0x04
__vo uint32_t EXTICR[4]; //address offset 0x08-0x14
__vo uint32_t CFGR; //address offset 0x18
__vo uint32_t reserved2; //address offset 0x1C
__vo uint32_t CCCSR; //address offset 0x20
__vo uint32_t CCVR; //address offset 0x24
__vo uint32_t CCCR; //address offset 0x28
__vo uint32_t reserved3; //address offset 0x2C
__vo uint32_t ADC2ALT; //address offset 0x30
__vo uint32_t reserved4[60];//address offset 0x34 to 0x120
__vo uint32_t PKGR; //address offset 0x124
__vo uint32_t reserved5[118];//address offset 0x128- 0x2FC
__vo uint32_t UR0; //address offset 0x300
__vo uint32_t reserved6; //address offset 0x304
__vo uint32_t UR2;
__vo uint32_t UR3;
__vo uint32_t UR4;
__vo uint32_t UR5;
__vo uint32_t UR6;
__vo uint32_t UR7;
__vo uint32_t reserved7[3];
__vo uint32_t UR11;
__vo uint32_t UR12;
__vo uint32_t UR13;
__vo uint32_t UR14;
__vo uint32_t UR15;
__vo uint32_t UR16;
__vo uint32_t UR17;
}SYSCFG_RegDef_t;
/*
* PERIPHERAL DEFINATION (PERIPHERAL BASE ADDRESS TYPECASTED TO REGDEF)
*/
#define GPIOA ((GPIO_RegDef_t*)GPIOA_BASEADDR)
#define GPIOB ((GPIO_RegDef_t*)GPIOB_BASEADDR)
#define GPIOC ((GPIO_RegDef_t*)GPIOC_BASEADDR)
#define GPIOD ((GPIO_RegDef_t*)GPIOD_BASEADDR)
#define GPIOE ((GPIO_RegDef_t*)GPIOE_BASEADDR)
#define GPIOF ((GPIO_RegDef_t*)GPIOF_BASEADDR)
#define GPIOG ((GPIO_RegDef_t*)GPIOG_BASEADDR)
#define GPIOH ((GPIO_RegDef_t*)GPIOH_BASEADDR)
#define GPIOJ ((GPIO_RegDef_t*)GPIOJ_BASEADDR)
#define GPIOK ((GPIO_RegDef_t*)GPIOK_BASEADDR)
#define RCC ((RCC_RegDef_t*)RCC_BASEADDR)
#define EXTI ((EXTI_RegDef_t*)EXTI_BASEADDR)
#define SYSCFG ((SYSCFG_RegDef_t*)SYSCFG_BASEADDR)
/*
* CLOCK ENABLE MACRO FOR GPIOx PERIPHERAL
*/
#define GPIOA_PCLK_EN() (RCC->AHB4ENR |= (1<<0))
#define GPIOB_PCLK_EN() (RCC->AHB4ENR |= (1<<1))
#define GPIOC_PCLK_EN() (RCC->AHB4ENR |= (1<<2))
#define GPIOD_PCLK_EN() (RCC->AHB4ENR |= (1<<3))
#define GPIOE_PCLK_EN() (RCC->AHB4ENR |= (1<<4))
#define GPIOF_PCLK_EN() (RCC->AHB4ENR |= (1<<5))
#define GPIOG_PCLK_EN() (RCC->AHB4ENR |= (1<<6))
#define GPIOH_PCLK_EN() (RCC->AHB4ENR |= (1<<7))
#define GPIOJ_PCLK_EN() (RCC->AHB4ENR |= (1<<9))
#define GPIOK_PCLK_EN() (RCC->AHB4ENR |= (1<<10))
/*
* CLOCK ENABLE MACRO FOR I2Cx PERIPHERAL
*/
#define I2C1_PCLK_EN() (RCC->APB1LENR |= (1<<21))
#define I2C2_PCLK_EN() (RCC->APB1LENR |= (1<<22))
#define I2C3_PCLK_EN() (RCC->APB1LENR |= (1<<23))
#define I2C5_PCLK_EN() (RCC->APB1LENR |= (1<<25))
/*
* CLOCK ENABLE MACRO FOR SPIx PERIPHERAL
*/
#define SPI2_PCLK_EN() (RCC->APB1LENR |= (1<<14))
/*
* CLOCK ENABLE MACRO FOR USARTx PERIPHERAL
*/
#define USART2_PCLK_EN() (RCC->APB1LENR |= (1<<17))
/*
* CLOCK ENABLE MACRO FOR UARTx PERIPHERAL
*/
#define UART4_PCLK_EN() (RCC->APB1LENR |= (1<<19))
/*
* CLOCK ENABLE MACRO FOR SYSCONFIG PERIPHERAL
*/
#define SYSCFG_PCLK_EN() (RCC->APB4ENR |= (1<<1))
/*
* CLOCK DISABLE MACRO FOR GPIOx PERIPHERAL
*/
#define GPIOA_PCLK_DI() (RCC->AHB4ENR &=~(1<<0))
#define GPIOB_PCLK_DI() (RCC->AHB4ENR &=~(1<<1))
#define GPIOC_PCLK_DI() (RCC->AHB4ENR &=~(1<<2))
#define GPIOD_PCLK_DI() (RCC->AHB4ENR &=~(1<<3))
#define GPIOE_PCLK_DI() (RCC->AHB4ENR &=~(1<<4))
#define GPIOF_PCLK_DI() (RCC->AHB4ENR &=~(1<<5))
#define GPIOG_PCLK_DI() (RCC->AHB4ENR &=~(1<<6))
#define GPIOH_PCLK_DI() (RCC->AHB4ENR &=~(1<<7))
#define GPIOJ_PCLK_DI() (RCC->AHB4ENR &=~(1<<9))
#define GPIOK_PCLK_DI() (RCC->AHB4ENR &=~(1<<10))
/*
* CLOCK DISABLE MACRO FOR I2Cx PERIPHERAL
*/
#define I2C1_PCLK_DI() (RCC->APB1LENR &=~(1<<21))
#define I2C2_PCLK_DI() (RCC->APB1LENR &=~(1<<22))
#define I2C3_PCLK_DI() (RCC->APB1LENR &=~(1<<23))
#define I2C5_PCLK_DI() (RCC->APB1LENR &=~(1<<25))
/*
* CLOCK DISABLE MACRO FOR SPIx PERIPHERAL
*/
#define SPI2_PCLK_DI() (RCC->APB1LENR &=~(1<<14))
/*
* CLOCK DISABLE MACRO FOR USARTx PERIPHERAL
*/
#define USART2_PCLK_DI() (RCC->APB1LENR &=~(1<<17))
/*
* CLOCK DISABLE MACRO FOR UARTx PERIPHERAL
*/
#define UART4_PCLK_DI() (RCC->APB1LENR &=~(1<<19))
/*
* MACROS TO RESET THE GPIOx PERIPHERALS
*/
#define GPIOA_REG_RESET() do{(RCC->AHB4RSTR |=(1<<0)) ; (RCC->AHB4RSTR &=~(1<<0));}while(0)
#define GPIOB_REG_RESET() do{(RCC->AHB4RSTR |=(1<<1)) ; (RCC->AHB4RSTR &=~(1<<1));}while(0)
#define GPIOC_REG_RESET() do{(RCC->AHB4RSTR |=(1<<2)) ; (RCC->AHB4RSTR &=~(1<<2));}while(0)
#define GPIOD_REG_RESET() do{(RCC->AHB4RSTR |=(1<<3)) ; (RCC->AHB4RSTR &=~(1<<3));}while(0)
#define GPIOE_REG_RESET() do{(RCC->AHB4RSTR |=(1<<4)) ; (RCC->AHB4RSTR &=~(1<<4));}while(0)
#define GPIOF_REG_RESET() do{(RCC->AHB4RSTR |=(1<<5)) ; (RCC->AHB4RSTR &=~(1<<5));}while(0)
#define GPIOG_REG_RESET() do{(RCC->AHB4RSTR |=(1<<6)) ; (RCC->AHB4RSTR &=~(1<<6));}while(0)
#define GPIOH_REG_RESET() do{(RCC->AHB4RSTR |=(1<<7)) ; (RCC->AHB4RSTR &=~(1<<7));}while(0)
#define GPIOJ_REG_RESET() do{(RCC->AHB4RSTR |=(1<<9)) ; (RCC->AHB4RSTR &=~(1<<9));}while(0)
#define GPIOK_REG_RESET() do{(RCC->AHB4RSTR |=(1<<10)); (RCC->AHB4RSTR &=~(1<<10));}while(0)
/*
* MACRO FOR GPIO BASEADDR TO CODE
*/
#define GPIO_BASEADDR_TO_CODE(X) ((X==GPIOA)?0:\
(X==GPIOB)?1:\
(X==GPIOC)?2:\
(X==GPIOD)?3:\
(X==GPIOE)?4:\
(X==GPIOF)?5:\
(X==GPIOG)?6:\
(X==GPIOH)?7:\
(X==GPIOJ)?8:\
(X==GPIOK)?9:0)
/*
* IRQ(Interrupt Request) Numbers of STM32h7x MCU
* NOTE: update these macros with valid values according to your MCU
* TODO: You may complete this list for other peripherals
*/
#define IRQ_NO_EXTI0 6
#define IRQ_NO_EXTI1 7
#define IRQ_NO_EXTI2 8
#define IRQ_NO_EXTI3 9
#define IRQ_NO_EXTI4 10
#define IRQ_NO_EXTI9_5 23
#define IRQ_NO_EXTI15_10 40
/*
* macros for all the possible priority levels
*/
#define NVIC_IRQ_PRI0 0
#define NVIC_IRQ_PRI15 15
/*
* some generic macros
*/
#define ENABLE 1
#define DISABLE 0
#define SET ENABLE
#define RESET DISABLE
#define GPIO_PIN_SET SET
#define GPIO_PIN_RESET RESET
#endif /* INC_STM32H7XX_H_ */