STM32H563 ADC Prescaler

[tw1]

Hello

I am a little confused by the clock prescaler for the ADC.

I would like to run the 12 bit ADC at 75Mhz for the maximum sampling frequency. However, with a prescaler of 1 the value I get is stuck at 4095. Only if I were to put a prescaler of 2 for any ADC frequency would I get a proper output from the ADC but of course the sample rate is reduced.

It appears the maximum value I can have the ADC running at with the DAC is 125Mhz with a prescaler of 2, which is below 5msps.

What am I missing here?

 

[TDK]

What is the board or full chip number you are using? What pin are you using? Suspect it may not be a fast channel.

[tw1]

STM32H563ZIT6. This is the nucleo-144 evaluation board.

Im using both ADC1 IN0 and ADC2 IN3, both of which should be fast channels assuming I have read properly. 

I wouldnt believe my issue would be affected by fast or slow channels. For example I set the ADC clock to 10Mhz  or increased the sampling time with the same issue.

Attached is how I have configured the ADC + DMA:

My program essentially does this:

uint16_t adc_buff[ADC_BUFF];

int convcomplete=0;

int n=0;

...

HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buff, ADC_BUFF);

while(1){

 if(convcomplete==1){

sprintf(msg, "%hu\r\n", adc_buff[n]);
CDC_Transmit_FS((uint8_t *)msg, strlen(msg));
convcomplete=0;
n++;
if(n==ADC_BUFF){
n=0;
}
 }

}

void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc){

 convcomplete=1;

}

[tw1]

I guess I should further ask, why is it that the ADC/ DAC clock is limited to 125Mhz when having both the ADC and DAC active at the same time? With only the ADC active I am able to set the clock up to 250Mhz with a prescaler of 4.
Considering I am using PLL2 I can change it in PeriphCommonClock_Config() to be at 150Mhz and set the ADC prescaler to 2 in which all seems to work?